Circuit designing apparatus, circuit designing method and timing distribution apparatus

Claim 2

A timing distribution apparatus for use for hierarchical design, comprising: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers, and each of which for receiving block information regarding a function of a circuit from a respective timing information database having netlist information regarding a wiring line scheme and outputting a respective timing distribution value obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager for dynamically changing connections between said plurality of timing distribution production sections and transmitting and receiving modification information regarding the respective timing distribution value to and from said plurality of timing distribution production sections, wherein said inter-hierarchical layer association manager receives a timing distribution specification changing request transmitted from the respective timing information database, extracts the other timing information databases on which the timing distribution specification change has an influence, and inquires from the pertaining timing information database whether a change of the respective timing distribution value is permissible, and outputs, when a response representing that a change of the respective distribution value is permissible is received from the pertaining timing information database, to the one timing information database a notification that a change of the respective timing distribution value is permissible, and updates, when the respective timing distribution value is changed, a higher hierarchical layer entity than the hierarchical layer in which the respective timing distribution value is changed.

Claim 3

The timing distribution apparatus as claimed in claim 1 , wherein said timing distribution production sections are formed as agents individually provided corresponding to the plurality of design hierarchical layers and having a hierarchical layer entity having design information and program data for processing the design information, and said inter-hierarchical layer association manager is formed as a manager connected to said timing distribution production sections for transmitting and receiving information regarding the respective timing distribution value individually to and from the plurality of design hierarchical layers.

Claim 4

A timing distribution apparatus for use for hierarchical design, comprising: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers, and each of which for receiving block information regarding a function of a circuit from a respective timing information database having netlist information regarding a wiring line scheme and outputting the respective timing distribution value obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager for dynamically changing connections between said plurality of timing distribution production sections and transmitting and receiving modification information regarding the respective timing distribution value to and from said plurality of timing distribution sections, wherein said timing distribution production sections are formed as agents individually provided corresponding to the plurality of design hierarchical layers and having a hierarchical layer entity having design information and program data for processing the design information, and said inter-hierarchical layer association manager is formed as a manager connected to said timing distribution production sections for transmitting and receiving information regarding the respective timing distribution value individually to and from the plurality of design hierarchical layers, wherein each of said timing distribution production sections includes: a logic/constraint information storage section for storing logic/constraint information having at least a netlist regarding a source code of a design language, the block information and constraint information regarding wiring line; a floor planning section connected to said logic/constraint information storage section for distributing timings based on a floor plan regarding arrangement of circuit elements and wiring lines between the circuit elements to perform provisional wiring line; a timing information storage section connected to said floor planning section for storing the netlist information; and a distribution manager connected to said logic/constraint information storage section and said timing information storage section for outputting the delay value based on at least the netlist information.

Claim 5

A timing distribution apparatus for use for hierarchical design, comprising: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers, and each of which for receiving block information regarding a function of a circuit from a respective timing information database having netlist information regarding a wiring line scheme and outputting the respective timing distribution value obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager for dynamically changing connections between said plurality of timing distribution production sections and transmitting and receiving modification information regarding the respective timing distribution value to and from said plurality of timing distribution sections, wherein said timing distribution production sections are formed as agents individually provided corresponding to the plurality of design hierarchical layers and having a hierarchical layer entity having design information and program data for processing the design information, and said inter-hierarchical layer association manager is formed as a manager connected to said timing distribution production sections for transmitting and receiving information regarding the respective timing distribution value individually to and from the plurality of design hierarchical layers, wherein each of said timing distribution production sections includes: a logic/constraint information storage section for storing logic/constraint information having at least a netlist regarding a source code of a design language, the block information and constraint information regarding wiring line; a floor planning section connected to said logic/constraint information storage section for distributing timings based on a floor plan regarding arrangement of circuit elements and wiring lines between the circuit elements to perform provisional wiring line; a timing information storage section connected to said floor planning section for storing the netlist information; and a distribution manager connected to said logic/constraint information storage section and said timing information storage section for outputting the delay value based on at least the netlist information.

Claim 6

The timing distribution apparatus as claimed in claim 3 , wherein said floor planning section includes: an arrangement processing section connected to said logic/constraint information storage section for presenting a portion with regard to which a distribution value as attribute information can be improved and modified based on a slack from the constraint information and storing arrangement information originating from the delay element information; an actual wiring and provisional wiring execution section connected to said arrangement processing section for performing association with actual wiring and provisional wiring,: and outputting wiring information; a wiring information storage section connected to said actual wiring and provisional wiring execution section for storing the wiring information; a physical technology information storage section for storing physical technology information including at least delay values per unit length corresponding to wiring line layers and load capacities per unit length in order to output the timing information; and a conversion section connected to said wiring information storage section and said physical technology information storage; section for converting the wiring information into a delay value based on the delay length and the load capacity and outputting the delay value.

Claim 7

The timing distribution apparatus as claimed in claim 4 , wherein said actual wiring and provisional wiring execution section performs wiring using both of actual wiring which requires long calculation time and provisional wiring which requires short calculation time and extracts the respective timing distribution value.

Claim 8

The timing distribution apparatus according to claim 4 , wherein said actual wiring and provisional wiring execution section includes: a Manhattan length provisional wiring section for performing Manhattan length provisional wiring for both of a printed circuit board and a large scale integrated circuit based on a result of arrangement of an arrangement supporting section which presents a portion with which the distribution value as attribute information can be improved and modified based on a slack from constraint information; an oblique Manhattan length provisional wiring section for performing provisional wiring using oblique wiring wherein a wiring line is located obliquely with respect to an edge of the printed circuit board based on the arrangement result; and an actual wiring association section for performing wiring for the printed circuit board and the large scale integrated circuit.

Claim 9

The timing distribution apparatus as claimed in claim 6 , wherein said actual wiring and provisional wiring execution section performs the provisional wiring based on the Manhattan length provisional wiring, the oblique Manhattan length provisional wiring and the actual wiring.

Claim 10

The timing distribution apparatus as claimed in claim 6 , wherein said actual wiring and provisional wiring execution section performs actual wiring based on a margin calculated with regard to the timing distribution value obtained by the provisional wiring and a wiring line congestion degree representative of the density of the wiring lines.

Claim 11

The timing distribution apparatus as claimed in claim 6 , wherein said actual wiring and provisional wiring execution section outputs information for analysis regarding information which is insufficient in the actual wiring so as to allow cooperation with another designing apparatus which uses another computer which can perform only the actual wiring.

Claim 12

The timing distribution apparatus as claimed in claim 6 , wherein said actual wiring and provisional wiring execution section performs the provisional wiring and the actual wiring based on at least a region in which wiring is inhibited and the wiring line congestion degree.

Claim 13

The timing distribution apparatus as claimed in claim 6 , wherein said actual wiring and provisional wiring execution section discriminates based on a clock frequency used as a constraint condition whether arrival within time within which arrival is essentially required is possible and issues, if the arrival is impossible, an instruction to insert at least one of a buffer and a flip-flop into the netlist information between a plurality of circuit blocks.

Claim 14

The timing distribution apparatus as claimed in claim 6 , wherein said actual wiring and provisional wiring execution section arranges terminals included in circuit blocks based on the: constraint information.

Claim 15

The timing distribution apparatus as claimed in claim 4 , wherein said actual wiring and provisional wiring execution section reads out the delay values and the load capacities of a selected hierarchical layer from said physical technology information storage section, varies the delay time per unit wiring line length and distributes the delay time.

Claim 16

The timing distribution apparatus as claimed in claim 4 , wherein said physical technology information storage section stores the wiring line length and the delay value per unit length and load capacity per unit length in a mutually associated relationship.

Claim 17

The timing distribution apparatus as claimed in claim 3 , wherein said floor planning section changes a wiring line width in a circuit block while the actual wiring or the provisional wiring is proceeding.

Claim 18

The timing distribution apparatus as claimed in claim 3 , wherein each of said timing distribution production sections further includes a waveform analysis information production section for producing information for waveform analysis of a printed circuit board from input/output buffer information of a hierarchical layer of a large scale integration circuit.

Claim 19

The timing distribution apparatus as claimed in claim 3 , wherein each of said timing distribution production sections outputs the timing distribution value based on another timing specification set in advance and the timing distributed by said floor planning section.

Claim 20

The timing distribution apparatus as claimed in claim 3 , wherein said floor planning section changes at least one of a scale and a shape of the circuit blocks while the actual wiring or the provisional wiring is proceeding.

Claim 21

The timing distribution apparatus as claimed in claim 3 , wherein each of said timing distribution production sections reads in timing distribution values back annotated from logical design or layout examination using the source code.

Claim 22

The timing distribution apparatus as claimed in claim 3 , wherein each of said timing distribution production sections further includes an annotator for writing information arising from the timing distribution values into the source code.

Claim 23

The timing distribution apparatus as claimed in claim 20 , wherein said annotator writes netlist information regarding a wiring scheme into the source code.

Claim 24

The timing distribution apparatus as claimed in claim 3 , wherein said distribution manager includes: a distribution editor connected to said logic/constraint information storage section for distributing timings; a database reference registration section connected to said distribution editor, said logic/constraint information storage: section and said timing information storage section for outputting the netlist information; a self hierarchical layer timing information database outputting and other hierarchical layer timing information database reflection section for inputting and outputting timing distribution information of a hierarchical layer to which said distribution manager belongs and timing distribution information of the other hierarchical layer or layers; and an arbitration control section for performing arbitration.

Claim 25

The timing distribution apparatus as claimed in claim 3 , wherein said distribution manager calculates a skew representative of a phase difference of an arrival time of a signal based on, one or those of wiring line paths of netlist information regarding a wiring scheme which are other than a common wiring line path or paths.

Claim 26

The timing distribution apparatus as claimed in claim 3 , wherein said distribution manager applies a name representative of a wiring line scheme as a sub signal name to each of the wiring line paths.

Claim 27

The timing distribution apparatus as claimed in claim 3 , wherein said distribution manager applies a sub signal name in an associated relationship with a fan-out number.

Claim 28

The timing distribution apparatus as claimed in claim 3 , wherein said distribution manager displays a gradation of a wired portion corresponding to the value of the constraint information in color on an operation screen.

Claim 29

The timing distribution apparatus as claimed in claim 3 , wherein said distribution manager displays the timing distribution values and a range in value within which the timing can be distributed on a figure which shows the circuit blocks.

Claim 30

A timing distribution apparatus for use for hierarchical design, comprising: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers, and each of which for receiving block information regarding a function of a circuit from a respective timing information database having netlist information regarding a wiring line scheme and outputting the respective timing distribution value obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager for dynamically changing connections between said plurality of timing distribution production sections and transmitting and receiving modification information regarding the respective timing distribution value to and from said plurality of timing distribution sections, wherein said timing distribution production sections are formed as agents individually provided corresponding to the plurality of design hierarchical layers and laying a hierarchical layer entity having design information and program data for processing the design information, and said inter-hierarchical layer association manager is formed as a manager connected to said timing distribution production sections for transmitting and receiving information regarding the respective timing distribution value individually to and from the plurality of design hierarchical layers, wherein said inter-hierarchical layer association manager extracts a circuit block whose timing information data is insufficient and inputs the extracted circuit block to said associated timing information database, and notifies a designer of the circuit block whose timing information data is insufficient.

Claim 31

A timing distribution apparatus for use for hierarchical design, comprising: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers, and each of which for receiving block information regarding a function of a circuit from a respective timing information database having netlist information regarding a wiring line scheme and outputting the respective timing distribution value obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager for dynamically changing connections between said plurality of timing distribution production sections and transmitting and receiving modification information regarding the respective timing distribution value to and from said plurality of timing distribution sections, wherein said timing distribution production sections are formed as agents individually provided corresponding to the plurality of design hierarchical layers and laying a hierarchical layer entity having design information and program data for processing the design information, and said inter-hierarchical layer association manager is formed as a manager connected to said timing distribution production sections for transmitting and receiving information regarding the respective timing distribution value individually to and from the plurality of design hierarchical layers, wherein said inter-hierarchical layer association manager extracts a circuit block whose timing information data is insufficient and inputs the extracted circuit block to said associated timing information database, and notifies a designer of the circuit block whose timing information data is insufficient.

Claim 32

A timing distribution apparatus for use for hierarchical design, comprising: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers, and each of which for receiving block information regarding a function of a circuit from a respective timing information database having netlist information regarding a wiring line scheme and outputting the respective timing distribution value obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager for dynamically changing connections between said plurality of timing distribution production sections and transmitting and receiving modification information regarding the respective timing distribution value to and from said plurality of timing distribution sections, wherein said timing distribution production sections are formed as agents individually provided corresponding to the plurality of design hierarchical layers and having a hierarchical layer entity having design information and program data for processing the design information, and said inter-hierarchical layer association manager is formed as a manager connected to said timing distribution production sections for transmitting and receiving information regarding the respective timing distribution value individually to and from the plurality of design hierarchical layers, wherein said inter-hierarchical layer association manager changes the combination of said plurality of distribution managers.

Claim 33

A timing distribution apparatus for use for hierarchical design, comprising: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers, and each of which for receiving block information regarding a function of a circuit from a respective timing information database having netlist information regarding a wiring line scheme and outputting the respective timing distribution value obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager for dynamically changing connections between said plurality of timing distribution production sections and transmitting and receiving modification information regarding the respective timing distribution value to and from said plurality of timing distribution sections, wherein said timing distribution production sections are formed as agents individually provided corresponding to the plurality of design hierarchical layers and having a hierarchical layer entity having design information and program data for processing the design information, and said inter-hierarchical layer association manager is formed as a manager connected to said timing distribution production sections for transmitting and receiving information regarding the respective timing distribution value individually to and from the plurality of design hierarchical layers, wherein said inter-hierarchical layer association manager changes the combination of said plurality of distribution managers.

Claim 34

A computer-readable recording medium on which a program is recorded, the program causing a computer to function as: a plurality of timing distribution production sections individually provided corresponding to plurality of design hierarchical layers, and each of which for receiving block information regarding functions of a circuit from a respective timing information database having netlist information regarding a wiring line scheme and outputting a respective timing distribution value obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager connected to said plurality of timing distribution production sections for transmitting and receiving modification information regarding the respective timing distribution value timing distribution values to and from said plurality of timing distribution production sections, wherein said inter-hierarchical layer association manager receives a timing distribution specification changing request transmitted from the respective timing information database, extracts other timing information databases on which the timing of distribution specification change has an influence, and inquires from the pertaining timing information database whether a change of the respective timing distribution value is permissible, and outputs, when a response representing that a change of the respective timing distribution value is permissible is received from the pertaining timing information database, to the respective timing information database a notification that a change of the respective timing distribution value is permissible, and updates, when the respective timing distribution value is changed, a higher hierarchical layer entity than the hierarchical layer in which the respective timing distribution value is changed.

Claim 35

A computer-readable recording medium on which a program is recorded, the program causing a computer to function as: a plurality of timing distribution production sections individually provided corresponding to plurality of design hierarchical layers, and each of which for receiving block information regarding functions of a circuit from a respective timing information database having netlist information regarding a wiring line scheme and outputting a respective timing distribution value obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager connected to said plurality of timing distribution production sections for transmitting and receiving modification information regarding the respective timing distribution value timing distribution values to and from said plurality of timing distribution production sections, wherein said inter-hierarchical layer association manager receives a timing distribution specification changing request transmitted from the respective timing information database, extracts other timing information databases on which the timing of distribution specification change has an influence, and inquires from the pertaining timing information database whether a change of the respective timing distribution value is permissible, and outputs, when a response representing that a change of the respective timing distribution value is permissible is received from the pertaining timing information database, to the respective timing information database a notification that a change of the respective timing distribution value is permissible, and updates, when the respective timing distribution value is changed, a higher hierarchical layer entity than the hierarchical layer in which the respective timing distribution value is changed.