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US6690214B2
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DLL circuit and DLL control method
Assignee: Longitude Licensing Ltd
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Filing: 2001-07-12
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Granted: 2004-02-10
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Expires: 2021-07-12
Abstract
Abstract A delay locked loop (DLL) circuit ( 10 ) can include first phase decision circuit ( 1 ), a second phase decision circuit ( 2 ), an arbitrary phase generator circuit ( 3 ), and a variable pulse width circuit ( 4 ). First phase decision circuit ( 1 ) may receive an external clock signal (D 1 ) and an internal clock signal (D 3 ) and may generate a phase decision signal (D 4 ) that may indicate whether a first edge of internal clock signal (D 3 ) is to be sped-up or delayed. Arbitrary phase generator circuit ( 3 ) may provide a phase shifted signal based on phase decision signal (D 4 ). Second phase decision circuit ( 2 ) may receive external clock signal (D 1 ) and internal clock signal (D 3 ) and may generate a phase decision signal (D 5 ) that may indicate whether a second edge of internal clock signal (D 3 ) is to be sped-up or delayed. Variable pulse width circuit ( 4 ) may receive the phase shifted signal and delay a falling edge based on phase decision signal (D 5 ).
Inventors
- 👤 Kazutaka Miyano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:46
CPC Classifications
H; H03; H03L; H03L7/00; H03K; H03K5/00; H03K5/156; H03K5/1565; H03K5/01; H03K5/08; H03K5/13; H03K5/133; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/085; H03L7/087; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
185 words
A delay locked loop (DLL) circuit, comprising: an external clock having a first external clock edge and a second external clock edge; an internal clock having a first internal clock edge and a second internal clock edge; a first phase decision circuit coupled to receive the external clock and the internal clock and providing a first phase decision signal based on a phase relationship between the first external clock edge and the first internal clock edge; a second phase decision circuit coupled to receive the external clock and the internal clock and providing a second phase decision signal based on a phase relationship between the second external clock edge and the second internal clock edge; an arbitrary phase generator circuit coupled to receive the first phase decision signal and provide an adjusted reference clock having a phase based on the value of the first phase decision signal; and a variable pulse width circuit coupled to receive the second phase decision signal and the adjusted reference clock and provide the internal clock having a pulse width based on the value of the second phase decision signal.
Claim 2
Dependent Claim
185 words
A delay locked loop (DLL) circuit, comprising: an external clock having a first external clock edge and a second external clock edge; an internal clock having a first internal clock edge and a second internal clock edge; a first phase decision circuit coupled to receive the external clock and the internal clock and providing a first phase decision signal based on a phase relationship between the first external clock edge and the first internal clock edge; a second phase decision circuit coupled to receive the external clock and the internal clock and providing a second phase decision signal based on a phase relationship between the second external clock edge and the second internal clock edge; an arbitrary phase generator circuit coupled to receive the first phase decision signal and provide an adjusted reference clock having a phase based on the value of the first phase decision signal; and a variable pulse width circuit coupled to receive the second phase decision signal and the adjusted reference clock and provide the internal clock having a pulse width based on the value of the second phase decision signal.
Claim 3
Dependent Claim
38 words
The DLL circuit according to claim 1 , wherein: the first internal clock edge is substantially locked with the first external clock edge; and the second internal clock edge is substantially locked with the second external clock edge.
Claim 4
Dependent Claim
46 words
The DLL circuit according to claim 2 , wherein: the first internal clock edge is a positive edge; the first external clock edge is a positive edge; the second internal clock edge is a negative edge; and the second external clock edge is a negative edge.
Claim 5
Dependent Claim
46 words
The DLL circuit according to claim 2 , wherein: the first internal clock edge is a negative edge; the first external clock edge is a negative edge; the second internal clock edge is a positive edge; and the second external clock edge is a positive edge.
Claim 6
Dependent Claim
35 words
The DLL circuit according to claim 1 , wherein: the arbitrary phase generator circuit is coupled to receive a reference clock and provide the adjusted reference clock that is phase shifted from the reference clock.
Claim 7
Dependent Claim
91 words
The DLL circuit according to claim 5 , wherein the arbitrary phase generator circuit includes: a phase clock signal generator circuit coupled to receive the reference clock and provide a plurality of phase shifted clock signals; a phase control circuit coupled to receive the first phase decision signal and providing at least one clock select signal; and a clock signal select circuit coupled to receive the at least one clock select signal and select at least one of the plurality of phase shifted clock signals to generate the adjusted phase clock.
Claim 8
Dependent Claim
61 words
A delay locked loop (DLL) control method, comprising the steps of: comparing a first phase of an external clock with a first phase of an internal clock and generating a first comparison result; generating an adjusted clock from a reference clock based on the first comparison result; and adjusting the pulse width of the adjusted clock to generate the internal clock.
Claim 9
Dependent Claim
61 words
A delay locked loop (DLL) control method, comprising the steps of: comparing a first phase of an external clock with a first phase of an internal clock and generating a first comparison result; generating an adjusted clock from a reference clock based on the first comparison result; and adjusting the pulse width of the adjusted clock to generate the internal clock.
Claim 10
Dependent Claim
56 words
The DLL control method according to claim 7 , wherein: adjusting the pulse width of the adjusted clock includes comparing a second phase of the external clock with a second phase of the internal clock and generating a second comparison result; and adjusting the pulse width of the adjusted clock based on the second comparison result.
Claim 11
Dependent Claim
55 words
The DLL control method according to claim 8 , wherein: comparing the second phase of the external clock with the second phase of the internal clock includes enabling a second phase decision circuit based on a second internal clock edge to generate the second comparison result based on the logic level of the external clock.
Claim 12
Dependent Claim
36 words
The DLL control method according to claim 7 , wherein: adjusting the pulse width of the adjusted clock includes modifying the propagation delay of a delay circuit by adjusting the impedance of a controllable impedance path.
Claim 13
Dependent Claim
35 words
The DLL control method according to claim 7 , wherein: generating an adjusted clock from a reference clock includes generating complementary clock signals phase shifted from the reference clock according to the first comparison result.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2007-02-09 | 2007-08-11 | 2008-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-02-09 | 2011-08-11 | 2012-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-02-09 | 2015-08-11 | 2016-02-10 | $7700.00 | Window Closed / Lapsed |