US6731652B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic packet processor architecture
Assignee: Adva Optical Networking Ltd
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Filing: 2001-03-09
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Granted: 2004-05-04
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Expires: 2021-03-09
Abstract
Abstract The packet processor system has a port for receiving packets from a first network. A line interface unit is connected to the port for determining the types of packets that are received by the port. A generic pipeline stage assembly is connected to the line interface unit and includes a plurality of generic pipeline stages each having a request engine for sending lookup requests to a lookup engine and a modifier engine for receiving lookup results from the lookup engine. A packet memory is connected to a last generic pipeline stage of the generic pipeline stage assembly and an output line interface unit is connected to the packet memory and a second network.
Inventors
- 👤 Lars H{dot over (a)}kan Ramfelt
- 👤 Simon Assouad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:09
CPC Classifications
H; H04; H04L; H04L45/00; H04L45/50; H04L45/502; H04L49/00; H04L49/15; H04L49/1515; H04L49/1546; H04L49/30; H04L49/3018; H04L49/35; H04L49/351; H04L49/354
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
196 words
A method for processing a packet in a packet processor having a line interface unit, comprising: the line interface unit receiving a packet; converting the packet into a task comprising the packet and a task overhead information; sending the task overhead information to a first request engine of a first pipeline stage in a generic routing pipeline assembly; sending the packet to a packet buffer; the first request engine receiving the task overhead information and preparing a first lookup request based on information in the task overhead information; the first request engine sending the first lookup request to a lookup engine; the lookup engine receiving the first lookup request and looking up new information based on the first lookup request; the lookup engine retrieving a first lookup result comprising the new information and sending the first lookup result to a first modifier engine of the first pipeline stage; the first modifier engine retrieving the packet from the packet buffer; the first modifier engine modifying the packet, based on the first lookup result, to a modified packet; and the first modifier engine sending the modified packet to a second request engine of a second subsequent pipeline stage.
Claim 2
Independent Claim
196 words
A method for processing a packet in a packet processor having a line interface unit, comprising: the line interface unit receiving a packet; converting the packet into a task comprising the packet and a task overhead information; sending the task overhead information to a first request engine of a first pipeline stage in a generic routing pipeline assembly; sending the packet to a packet buffer; the first request engine receiving the task overhead information and preparing a first lookup request based on information in the task overhead information; the first request engine sending the first lookup request to a lookup engine; the lookup engine receiving the first lookup request and looking up new information based on the first lookup request; the lookup engine retrieving a first lookup result comprising the new information and sending the first lookup result to a first modifier engine of the first pipeline stage; the first modifier engine retrieving the packet from the packet buffer; the first modifier engine modifying the packet, based on the first lookup result, to a modified packet; and the first modifier engine sending the modified packet to a second request engine of a second subsequent pipeline stage.
Claim 3
Dependent Claim
37 words
The method according to claim 1 wherein the packet memory unit stores the packet and the descriptor so that the descriptor is associated with the packet and the packet buffer is contained in the first pipeline stage.
Claim 4
Dependent Claim
38 words
The method according to claim 1 wherein the method further comprising an output line interface retrieving the packet from the packet memory unit by reviewing a queue of descriptors associated with descriptors stored in the packet memory unit.
Claim 5
Dependent Claim
26 words
The method according to claim 3 wherein the method further comprising storing the descriptors in a buffer so that each descriptor is pointing to a packet.
Claim 6
Dependent Claim
34 words
The method according to claim 1 wherein the method further comprising an output line interface reviewing a descriptor's head pointer list so that a first descriptor is first processed by the output line interface.
Claim 7
Dependent Claim
41 words
The method according to claim 1 wherein the method further comprises providing the generic routing pipeline assembly with a last pipeline stage and the last pipeline stage updating a tail pointer list of the packet memory unit with a new descriptor.
Claim 8
Dependent Claim
168 words
A packet processor system, comprising: a receiving unit for receiving packets from a first network; a line interface unit connected to a port for classifying types of packets received by the port; a generic pipeline stage assembly connected to the line interface unit, the assembly comprising a generic pipeline stage having a request engine for sending lookup requests to a lookup engine and a modifier engine for receiving lookup results from the lookup engine, the lookup engine being connected to a database; a packet memory connected to the generic pipeline stage assembly; and an output line interface unit connected to the packet memory and a second network; and the lookup engine being connected to the generic pipeline stage assembly via a bus that is adapted to contain lookup requests from a plurality of pipeline stages of the generic pipeline stage assembly, the bus being in communication with a lookup arbiter of the lookup en me that distributes the lookup requests to lookup modules disposed in the lookup engine.
Claim 9
Dependent Claim
168 words
A packet processor system, comprising: a receiving unit for receiving packets from a first network; a line interface unit connected to a port for classifying types of packets received by the port; a generic pipeline stage assembly connected to the line interface unit, the assembly comprising a generic pipeline stage having a request engine for sending lookup requests to a lookup engine and a modifier engine for receiving lookup results from the lookup engine, the lookup engine being connected to a database; a packet memory connected to the generic pipeline stage assembly; and an output line interface unit connected to the packet memory and a second network; and the lookup engine being connected to the generic pipeline stage assembly via a bus that is adapted to contain lookup requests from a plurality of pipeline stages of the generic pipeline stage assembly, the bus being in communication with a lookup arbiter of the lookup en me that distributes the lookup requests to lookup modules disposed in the lookup engine.
Claim 10
Dependent Claim
24 words
The packet processor system according to claim 7 wherein the output line interface is connected to the generic pipeline stage assembly via a bus.
Claim 11
Dependent Claim
202 words
A packet processor system, comprising: a receiving unit comprising: a first port for receiving packets from a first network; a first line interface unit connected to the first port for classifying the packets received by the first port; a first generic pipeline stage assembly connected to the first line interface unit, the first assembly comprising a plurality of first generic pipeline stages each having a first request engine for sending lookup requests to a lookup engine and a first modifier engine for receiving lookup results from the lookup engine, the lookup engine being connected to a database; a transmit unit comprising: a second port for receiving packets from a second network; a second line interface unit connected to the second port; a second generic pipeline stage assembly connected to the second line interface unit, the second assembly comprising a plurality of second generic pipeline stages each having a second request engine for sending lookup requests to the lookup engine and a second modifier engine for receiving lookup results from the lookup engine; and a packet memory unit being connected to the first generic pipeline stage assembly via a first bus and to the second generic pipeline stage assembly via a second bus.
Claim 12
Dependent Claim
202 words
A packet processor system, comprising: a receiving unit comprising: a first port for receiving packets from a first network; a first line interface unit connected to the first port for classifying the packets received by the first port; a first generic pipeline stage assembly connected to the first line interface unit, the first assembly comprising a plurality of first generic pipeline stages each having a first request engine for sending lookup requests to a lookup engine and a first modifier engine for receiving lookup results from the lookup engine, the lookup engine being connected to a database; a transmit unit comprising: a second port for receiving packets from a second network; a second line interface unit connected to the second port; a second generic pipeline stage assembly connected to the second line interface unit, the second assembly comprising a plurality of second generic pipeline stages each having a second request engine for sending lookup requests to the lookup engine and a second modifier engine for receiving lookup results from the lookup engine; and a packet memory unit being connected to the first generic pipeline stage assembly via a first bus and to the second generic pipeline stage assembly via a second bus.
Claim 13
Dependent Claim
25 words
The packet processor system according to claim 9 wherein a first output line interface of the receive unit is connected to the packet memory unit.
Claim 14
Dependent Claim
23 words
The packet processor system according to claim 10 wherein the first output line interface is connected to the first generic pipeline stage assembly.
Claim 15
Dependent Claim
24 words
The packet processor system according to claim 9 wherein a second output line interface of the transmit unit is connected to the packet memory.
Claim 16
Dependent Claim
23 words
The packet processor system according to claim 12 wherein the second output line interface is connected to the second generic pipeline stage assembly.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-05-04 | 2007-11-03 | 2008-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-05-04 | 2011-11-03 | 2012-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-05-04 | 2015-11-03 | 2016-05-04 | $7700.00 | Window Closed / Lapsed |