Integrated circuit structure electrically isolated by a combination of amorphous silicon walls and isolating pn junction

Abstract

Abstract A PLANAR MONOCRYSTALLINE SILICON INTERATED CIRCUIT STRUCTURE HAVING A PLURALITY OF ELECTRICALLY ISOLATED POCKETS EXTENDING FROM THE SILICON SUBSTRATE SURFACE. EACH POCKET IS ISOLATED BY SIDEWALLS OF AMORPHOUS SILICON, FORMED BY THE BOMBARDMENT OF THE SILICON SUBSTRATE WITH SILICON IONS, LATERALLY ENCLOSING AN UPPER PORTION OF THE POCKET AND AN ISOLATING JUNCTION CONTINUOUS WITH SAID SIDEWALLS ENCLOSING THE LOWER PORTION OF THE POCKET. EACH ISOLATED POCKET IS SILICON OF ONE CONDUCTIVITY TYPE, AND SAID ISOLATING JUNCTION IS FORMED BY A SILICON REGION OF OPPOSITE CONDUCTIVITY TYPE ABUTTING THE POCKET. THE POCKETS CONTAIN REGIONS OF ONLY SAID OPPOSITE CONDUCTIVITY TYPE EXTENDING FROM THE SURFACE INTO THE POCKET BUT SPACED FROM SAID SIDEWALLS AND ISOLATING JUNCTIONS. THE STRUCTURE AVOIDS THE PROBLEM OF PARASITIC CAPACITANCES WHICH TEND TO OCCUR IN COMPLETELY JUNCION ISOLATED INTEGRATED CIRCUITS ALONG VERTICAL JUNCTIONS. BY LIMITING THE STRUCTURE TO ONLY REGIONS OF OPPOSITE CONDUCTIVITY TYPE DIFFUSED INTO POCKETS OF SAID ONE CONDUCTIVITY TYPE, THE STRUCTURE AVOIDS VERTICAL PN JUNCTIONS WHICH ARE ADJACENT TO EACH OTHER AND THUS, ARE SUBJECT TO PARASITIC CAPACITANCE EFFECTS.

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