Patent EP0031031A2 successfully refreshed from Google Patents.
EP0031031A2
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EP
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Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/output bus
Assignee: International Business Machines Corp
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Filing: 1980-11-18
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Granted: —
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Expires: 2000-11-18
Abstract
Abstract Serial storage interface apparatus for coupling a serial storage mechanism (1), such a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus (2). The date transfer circuitry includes and I/O controller (4) and a First-in-First-Out (FIFO) buffer storage mechanism (5). Speed control circuitry (6) is provided for causing the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the interface apparatus. This speed adjustment feature reduces the amount of data buffering required for interfacing a serial storage mechanism to an asynchronous variable response time I/O bus system.
Inventors
- 👤 Jerry Duane Dixon
- 👤 Robert Henry Farrell
- 👤 Francis Richard Koperda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 13:59
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F3/00; G06F3/007; G06F2205/00; G06F2205/06; G06F2205/061
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
78 words
- Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/ output (I/O) bus, characterized in that it comprises: data transfer circuitry for coupling the serial storage mechanism to the data processor I/O bus; and speed control circuitry responsive to the data transfer activity of the data transfer circuitry for causing the serial storage mechanism to operate at different speeds for different values of I/O bus availability to the serial storage interface apparatus.
Claim 2
Dependent Claim
78 words
- Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/ output (I/O) bus, characterized in that it comprises: data transfer circuitry for coupling the serial storage mechanism to the data processor I/O bus; and speed control circuitry responsive to the data transfer activity of the data transfer circuitry for causing the serial storage mechanism to operate at different speeds for different values of I/O bus availability to the serial storage interface apparatus.
Claim 3
Dependent Claim
56 words
- Serial storage interface apparatus in accordance with claim 1, characterized in that the speed control circuitry comprises bus utilization circuitry responsive to the data transfer activity of the data transfer circuitry for causing the serial storage mechanism to operate at different speeds for different values of I/O bus availability to the serial storage interface apparatus.
Claim 4
Dependent Claim
77 words
- Serial storage interface apparatus in accordance with claim 1 or 2, characterized in that: the interface apparatus further includes timing circuitry for supplying timing signals to the serial storage mechanism for controlling the operating speed thereof; and the speed control circuitry is responsive to the data transfer activity of the data transfer circuitry for causing the timing circuitry to operate at different speeds for different values of I/O bus availability to the serial storage interface apparatus.
Claim 5
Dependent Claim
70 words
- Serial storage interface apparatus in accordance with claim 1 or 2 or 3, characterized in that circuitry causes the serial storage mechanism to operate at a higher speed when the I/O bus is available to the serial storage interface apparatus a greater percentage of the time and at a lower speed when the I/O bus is available to the serial storage interface apparatus a lesser percentage of the time.
Claim 6
Dependent Claim
73 words
- Serial storage interface appartatus in accordance with claim 1 or 2 or 3, characterized in that the speed control circuitry causes the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the serial storage interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the serial storage interface apparatus.
Claim 7
Dependent Claim
97 words
- Serial storage interface apparatus in accordance with any of the preceding claims, characterized in that it comprises: a first-in-first-out (FIFO) buffer storage mechanism; first data transfer circuitry for coupling the FIFO buffer storage mechanism to the data processor I/O bus; second data transfer circuitry for coupling the FIFO buffer storage mechanism to the serial storage mechanism; and speed control circuitry responsive to the data transfer activity of the first data transfer circuitry for causing the serial storage mechanism to operate at different speeds for different values of I/O bus availability to the serial storage interface apparatus.
Claim 8
Dependent Claim
61 words
- Serial storage interface apparatus in accordance with claim 6, characterized in that the speed control circuitry is coupled to the FIFO buffer storage mechanism and is responsive to the amount of data in the FIFO buffer storage mechanism for causing the serial storage mechanism to operate at different speeds for different amounts of data in the FIFO buffer storage mechanism.
Claim 9
Dependent Claim
125 words
- Serial storage interface apparatus in accordance with claim 7, characterized in that: the serial storage interface apparatus is operated in a write mode for transferring data from the data processor to the serial storage mechanism via the FIFO buffer storage mechanism; the speed control circuitry causes the serial storage mechanism to operate at a higher speed when the amount of data in the FIFO buffer storage mechanism is equal to or greater than a predetermined value; the speed control circuitry causes the serial storage mechanism to operate at a lower speed when the amount of data in the FIFO buffer storage mechanism is less than this predetermined value; and the aforesaid predetermined value represents a nearly full condition of the FIFO buffer storage mechanism.
Claim 10
Dependent Claim
127 words
- Serial storage interface apparatus in accordance with claim 7 or 8, characterized in that: the serial storage interface apparatus is operated in a read mode for transferring data from the serial storage mechanism to the data processor via the FIFO buffer storage mechanism; the speed control circuitry causes the serial storage mechanism to operate at a higher speed when the amount of data in the FIFO buffer storage mechanism is less than a predetermined value; the speed control circuitry causes the serial storage mechanism to operate at a lower speed when the amount of data in the FIFO buffer storage mechanism is equal to or greater than this predetermined value; and the aforesaid predetermined value represents a nearly empty condition of the FIFO buffer storage mechanism.
Claim 11
Dependent Claim
107 words
- Serial storage interface appartaus in accordance with claim 6 or 7 or 8 or 9, characterized in that the FIFO buffer storage mechanism includes: multiple registers coupled in cascade and each capable of storing a unit of data; and circuitry for automatically moving data units successively stored into the input one of the FIFO registers from one register to the next so as to keep the data units in and as close to the output one of the FIFO registers as is possible, the data units being advanced one register position toward the output register each time a data unit is removed from such output register.
Claim 12
Dependent Claim
96 words
1 1.- Serial storage interface apparatus in accordance with claim 10, characterized in that: the FIFO buffer storage mechanism includes at least one status line, a status line being coupled to a FIF O register for providing signals indicative of the full/empty status of this register; and the speed control circuitry is responsive to the signals on the FIFO status line(s) for causing the serial storage mechanism to operate at one speed when a status line signal indicates a full status and at another and different speed when this status line signal indicates an empty status.
Claim 13
Dependent Claim
113 words
- Serial storage interface apparatus in accordance with claim 11, characterized in that: the serial storage interface apparatus is operated in a write mode for transferring data from the host processor to the serial storage mechanism via the FIFO buffer storage mechanism; at least one status line is coupled to at least one FIFO register closer to the input one of such FIFO registers; and the speed control circuitry is responsive to the signals on this status line for causing the serial storage mechanism to operate at a higher speed when the status line signal indicates a full status and at a lower speed when the status line signal indicates an empty status.
Claim 14
Dependent Claim
114 words
- Serial storage interface apparatus in accordance with claim 11 or 12, characterized in that: the serial storage interface apparatus is operated in a read mode for transferring data from the serial storage mechanism to the data processor via the FIFO buffer storage mechanism; at least one status line is coupled to at least one FIFO register closer to the output one of such registers; and the speed control circuitry is responsive to the signals on this status line for causing the serial storage mechanism to operate at a higher speed when the status line signal indicates an empty status and at a lower speed when the status line signal indicates a full status.
Claim 15
Dependent Claim
27 words
- Serial storage interface apparatus in accordance with any of the preceding claims, characterized in that the serial storage mechanism is a charge coupled device storage mechanism.
References Cited (Backward Citations)
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