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EP0032014A2
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Semiconductor memory circuit
Assignee: Fujitsu Ltd
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Filing: 1980-12-16
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Granted: —
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Expires: 2000-12-16
Abstract
Abstract The memory circuit has a right memory cell group MR and a left memory cell group ML between which word decoders (WDk) are located. Each word decoder is provided with left and right memory cell group selection and drive gates 31 L and 31R. One or other of gates 31L and 31R is closed in dependence upon a discrimination output provided from discrimination means which indicate to which memory cell group (ML or MR) a memory cell to be accessed belongs.
Inventors
- 👤 Hiroshi Shimada
- 👤 Keizo Aoyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 22:50
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417; G11C11/418; G11C5/00; G11C5/02; G11C5/025; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
113 words
A semiconductor memory circuit having right and left memory cell groups, and word decoders,corresponding to respective rows of the memory cell groups,located between the right and left memory cell groups, characterised in that the semiconductor memory circuit further comprises a respective right memory cell group selection and drive gate and a respective left memory cell group selection and drive gate provided for each word decoder, and discriminating means, for discriminating to which of the right and left memory cell groups a memory cell to be accessed belongs, either the right or the left memory cell group selection and drive gate being closed in dependence upon the discrimination result provided by the discriminating means.
Claim 2
Dependent Claim
113 words
A semiconductor memory circuit having right and left memory cell groups, and word decoders,corresponding to respective rows of the memory cell groups,located between the right and left memory cell groups, characterised in that the semiconductor memory circuit further comprises a respective right memory cell group selection and drive gate and a respective left memory cell group selection and drive gate provided for each word decoder, and discriminating means, for discriminating to which of the right and left memory cell groups a memory cell to be accessed belongs, either the right or the left memory cell group selection and drive gate being closed in dependence upon the discrimination result provided by the discriminating means.
Claim 3
Dependent Claim
30 words
A semiconductor memory circuit as claimed in claim 1, wherein the discrimination result is provided by a specified bit from among column address bits employed for accessing the memory cells.
Claim 4
Dependent Claim
36 words
A semiconductor memory circuit as claimed in claim 1 or 2, wherein each of the right and left memory cell group selection and drive gates comprises a transistor connected in series to the corresponding word line.
Claim 5
Dependent Claim
38 words
A semiconductor memory circuit according to claim 3, wherein, in each said gate, a further transistor, for preventing occurrence of a floating condition, is connected in parallel with the transistor connected in series to the corresponding word line.
References Cited (Backward Citations)
No citation records indexed.
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