Patent EP0036573A2 successfully refreshed from Google Patents.
EP0036573A2
Expired / Lapsed
EP
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Method for making a polysilicon conductor structure
Assignee: International Business Machines Corp
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Filing: 1981-03-12
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Granted: —
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Expires: 2001-03-12
Abstract
Abstract A method is described for eliminating abnormalities in a polycrystalline silicon integrated circuit structure, such as a silicon gate field effect transistor structure. The layer (30, 40) of polysilicon is deposited on an insulator coating (24, 38) which may be the thickness of the gate dielectric. The polycrystalline silicon is delineated by lithographic techniques and a reactive ion etching process to form the desired conductor structure. A thickness of the polycrystalline silicon of the order of tens of nanometers is left upon the insulator coating (24) where the masking layer has openings. This thin coating of polycrystalline silicon is then thermally oxidized together with the exposed sidewall of the polycrystalline silicon in the areas under the opaque parts of the masking layer to form silicon dioxide on the sidewall of the polycrystalline silicon structures. A directional reactive ion etching of the silicon dioxide removes all silicon dioxide formed by the thermal oxidation step from the horizontal silicon substrate while leaving the silicon dioxide on the vertical sidewall regions. The method prevents the formation of a poor grade of silicon dioxide under the edges of the polycrystalline silicon conductor structure.
Inventors
- 👤 Axel Stoffel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 09:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038; H10P; H10P76/00; H10P76/40; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/018; Y10S148/02; Y10S148/117; Y10S148/131; Y10S148/141; Y10S438/00; Y10S438/911
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
154 words
Method for making a polycrystalline silicon conductor structure in an integrated circuit, characterized by depositing a layer (30) of polycrystalline silicon upon a silicon substrate (22) covered by an insulator coating (24), masking the polycrystalline silicon (30) in areas where said conductor structure is desired, reactive ion etching said polycrystalline silicon (30) in unmasked areas until a thickness of said polycrystalline silicon of the order of tens of nanometers remains on said insulator coating (24), thermally oxidizing the unmasked polycrystalline silicon whereby the said thickness on said insulator coating is totally oxidized to silicon dioxide and the exposed sidewall of polycrystalline silicon located under the mask is oxidized without causing a silicon dioxide wedge formation under the said polycrystalline silicon located under the mask, and directionally reactive ion etching the said silicon dioxide to remove all silicon dioxide from the horizontal silicon substrate while leaving said silicon dioxide on the vertical said sidewall regions.
Claim 2
Dependent Claim
154 words
Method for making a polycrystalline silicon conductor structure in an integrated circuit, characterized by depositing a layer (30) of polycrystalline silicon upon a silicon substrate (22) covered by an insulator coating (24), masking the polycrystalline silicon (30) in areas where said conductor structure is desired, reactive ion etching said polycrystalline silicon (30) in unmasked areas until a thickness of said polycrystalline silicon of the order of tens of nanometers remains on said insulator coating (24), thermally oxidizing the unmasked polycrystalline silicon whereby the said thickness on said insulator coating is totally oxidized to silicon dioxide and the exposed sidewall of polycrystalline silicon located under the mask is oxidized without causing a silicon dioxide wedge formation under the said polycrystalline silicon located under the mask, and directionally reactive ion etching the said silicon dioxide to remove all silicon dioxide from the horizontal silicon substrate while leaving said silicon dioxide on the vertical said sidewall regions.
Claim 3
Dependent Claim
188 words
Method of claim 1 wherein a double polycrystalline structure is formed and further comprising thermally oxidizing an exposed silicon substrate (22) using a dry oxygen ambient to form the gate dielectric silicon dioxide layer (38) for a second layer (40) of polycrystalline silicon, depositing said second layer (40) of polycrystalline silicon onto said silicon dioxide layer (38), masking said second layer (40) of polycrystalline silicon in areas where said conductor structure is desired reactive ion etching said second polycrystalline silicon (40) in unmasked areas until a thickness of said polycrystalline silicon of the order of tens of .nanometers remains on said silicon dioxide, thermally oxidizing the said unmasked second polycrystalline silicon (40) whereby the said thickness on said insulator coating (38) is totally oxidized to silicon dioxide and the exposed sidewall of said second polycrystalline silicon located under the mask is oxidized without causing a silicon dioxide wedge formation under the said polycrystalline silicon located under the mask, and directionally reactive ion etching the said silicon dioxide to remove all silicon dioxide from the horizontal silicon substrate while leaving said silicon dioxide on the vertical said sidewall regions.
Claim 4
Dependent Claim
33 words
Method of claim 2 wherein the remaining portions of said polycrystalline silicon (30) and said second layer (40) of polycrystalline silicon are gate electrodes for metal-oxide-silicon field effect devices in said integrated circuit.
Claim 5
Dependent Claim
51 words
Method of claim 1 wherein said integrated circuit includes metal-oxide-silicon field effect devices, and further comprising diffusing (46) into said silicon substrate (22) in the appropriate areas to form sources and drain regions adjacent to the portions of said polycrystalline silicon (22) which are gate electrodes for said field effect devices.
Claim 6
Dependent Claim
44 words
Method of claim 3 and further comprising diffusing (46) into said silicon substrate (22) in the appropriate areas to form sources and drain regions adjacent to said gate electrodes of portions of said polycrystalline silicon (30) and said second layer (40) of polycrystalline silicon.
Claim 7
Dependent Claim
34 words
Method of claim 1 wherein said insulator coating (38) is silicon doxide and is formed with the desired thickness of the gate dielectric of field effect devices to be formed in said integrated circuit.
Claim 8
Dependent Claim
25 words
Method of claim 1 wherein the said thickness of said polycrystalline silicon (30, 40) after said reactive ion etching is greater than about 20 nm.
Claim 9
Dependent Claim
34 words
Method of claim 2 wherein the said thichnesses of said polycrystalline silicon (30, 40) and said second layer of polycrystalline silicon after said reactive ion etching steps are between about 20 and 100 nm.
Claim 10
Dependent Claim
24 words
Method of claim 1 wherein said silicon substrate contains regions of dielectric material which isolate certain regions of silicon from other regions of silicon.
References Cited (Backward Citations)
No citation records indexed.
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