Patent EP0041844A2 successfully refreshed from Google Patents.
EP0041844A2
Expired / Lapsed
EP
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Semiconductor integrated circuit devices
Assignee: Fujitsu Ltd
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Filing: 1981-06-05
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Granted: —
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Expires: 2001-06-05
Abstract
Abstract A semiconductor memory device has memory cells 2 and decoder circuitry 3 disposed centrally thereof. A ground line 7 min extends around the memory cells 2 and the decoder circuitry 3. Control circuits 41 to 46 are disposed beneath or outwardly of the ground line 7 min . Signal lines 5 min for connecting the control circuits to one another are disposed outwardly of the control circuits 41 to 46. A power line 6 min is in turn disposed outwardly of the signal lines 5 min . This layout can provide for a reduction in the number of bridges required.
Inventors
- 👤 Hideo Itoh
- 👤 Takahiko Yamauchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 18:42
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; G11C5/025; G11C5/14; H; H10; H10D; H10D89/00; H10D89/10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W72/00; H10W72/90; H10W72/931; H10W72/932
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
98 words
A semiconductor integrated circuit device, comprising a plurality of internal circuits disposed centrally thereof, a plurality of control circuits disposed in an area outwards of the internal circuits, a plurality of wiring lines connecting the control circuits and the internal circuits, a plurality of signal lines connecting the control circuits with one another, and at least one electric power supply line for supplying the internal circuits and the control circuits, wherein the signal lines and the said at least one power supply line are disposed outwardly.of the plurality of wiring lines connecting.the control circuits and the internal circuits.
Claim 2
Dependent Claim
98 words
A semiconductor integrated circuit device, comprising a plurality of internal circuits disposed centrally thereof, a plurality of control circuits disposed in an area outwards of the internal circuits, a plurality of wiring lines connecting the control circuits and the internal circuits, a plurality of signal lines connecting the control circuits with one another, and at least one electric power supply line for supplying the internal circuits and the control circuits, wherein the signal lines and the said at least one power supply line are disposed outwardly.of the plurality of wiring lines connecting.the control circuits and the internal circuits.
Claim 3
Dependent Claim
79 words
A semiconductor integrated circuit device, comprising a plurality of internal circuits disposed centrally thereof, a plurality of control circuits disposed in an area outwards of the internal circuits, a plurality of signal lines connecting the control circuits with one another, and a power supply line (which may be a ground line) for supplying the internal circuits and control circuits, wherein the power supply line is disposed inwardly of the signal lines and inwardly of or over the control circuits.
Claim 4
Dependent Claim
79 words
A semiconductor integrated circuit device, comprising a plurality of internal circuits disposed centrally thereof, a plurality of control circuits disposed in an area outwards of the internal circuits, a plurality of signal lines connecting the control circuits with one another, and a power supply line (which may be a ground line) for supplying the internal circuits and control circuits, wherein the power supply line is disposed inwardly of the signal lines and inwardly of or over the control circuits.
Claim 5
Dependent Claim
121 words
A semiconductor memory device, comprising a plurality of memory cells and decoder circuitry disposed centrally of the device, a first supply line disposed in an area outwards of the memory cells and decoder circuitry, at least one control circuit 'disposed in an area outwards of the memory cells and decoder circuitry, at least one signal line connected to a control circuit and/or connecting control circuits to one another, disposed in an area outwards of the first supply line and outwards of the said at least one control circuit, or disposed above the said at least one control circuit, and a second supply line disposed in an area outside the area in which the said at least one signal line is disposed.
Claim 6
Dependent Claim
121 words
A semiconductor memory device, comprising a plurality of memory cells and decoder circuitry disposed centrally of the device, a first supply line disposed in an area outwards of the memory cells and decoder circuitry, at least one control circuit 'disposed in an area outwards of the memory cells and decoder circuitry, at least one signal line connected to a control circuit and/or connecting control circuits to one another, disposed in an area outwards of the first supply line and outwards of the said at least one control circuit, or disposed above the said at least one control circuit, and a second supply line disposed in an area outside the area in which the said at least one signal line is disposed.
Claim 7
Dependent Claim
30 words
A device as claimed in claim 3, wherein the or each control circuit is disposed in an area outwards of the area in which the first supply line is disposed.
Claim 8
Dependent Claim
20 words
A device as claimed in claim 3, wherein the or each control circuit is disposed beneath the first supply line.
Claim 9
Dependent Claim
28 words
A device as claimed in claim 3, 4 or 5, wherein the first supply line is a ground line, and the second supply line is a power line.
Claim 10
Dependent Claim
28 words
A device as claimed in claim 3, 4 or 5, wherein the first supply line is a power line, and the second supply line is a ground line.
Claim 11
Independent Claim
28 words
A device as claimed in any one of claims 3 to 7, wherein the first supply line forms a complete loop around the memory cells and decoder circuitry.
Claim 12
Independent Claim
55 words
A device as claimed in any one of claims 3 to 7, wherein the first supply line forms a discontinuous loop, around the memory cells and decoder circuitry affording a gap therein through which connections are made from the second power supply line and from a signal line or signal lines to the decoder circuitry.
Claim 13
Independent Claim
69 words
A device as claimed in any one of claims 3 to 7, wherein the first supply line has free ends between which a gap is afforded through which connection is made from the second power supply line to the memory cells and decoder circuitry, and wherein the first. supply line is provided with a branch extending over the decoder circuitry for connection to a control circuit or control circuits.
Claim 14
Independent Claim
22 words
A device as claimed in any one of claims 3 to 10, wherein the or each signal line forms a complete loop.
References Cited (Backward Citations)
No citation records indexed.
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