Control method and apparatus for a plurality of memory units

Claim 2

Control method for a plurality of memory units of a data processing system, characterized in that a) a plurality of memory units (4,5) perform simultaneous writing or reading operations, b) one of the memory units (4;5) is selected for normal use, c) in the event of an error occurring during a write mode operation, a memory unit (4;5) without the error is immediately selected alternatively, and d) in the event of an error during a read mode operation, the selection is made, in response to the next clock pulse, to permit a retry from a processor (1;2).

Claim 3

A control apparatus for a plurality of memory units of a data processing system, particularly for carrying out the method according to Claim 1, comprising: a) a plurality of memory units (4,5), b) memory unit access means (12) to which said memory units (4,5) are accessible simultaneously, c) a plurality of error holding circuits (17,18), each of which continuously produces a status error signal in response to an error indication made by a status signal from a corresponding memory unit (4,5), d) control means (23) for generating a write command signal in response to a request from a processor (1;2), e) status selection commanding means (13) responsive to the write command signal from said control means (23), to a status error signal from one of the error holding circuits (17;18), and to a master designating signal externally given to designate one of said memory units (4,5) as a master memory unit, for producing a status selection signal simultaneously with the generation of said status error signal during a write mode operation, while producing a status selection signal in response to the next clock pulse after the generation of the status error signal during a read mode operation, and f) status selector means (14) for returning one of the status si nals given from the memory units (4,5) to the processor (1 ; 2) as a status notifying signal in response to the output of the status selection commanding means (13).

Claim 4

Apparatus according to Claim 2, further comprising: a) a priority identifying circuit (11), b) a memory access unit (12), c) status holding circuits (15,16), and d) holding circuits (10,19).

Claim 5

Apparatus according to Claim 2 or 3, characterized in that the status selection command unit (13) comprises a) a flip-flop (106) and b) a plurality of gates (100 to 105, 107 to 111, 117).

Claim 6

Apparatus according to Claim 3 or 4, characterized in that each holding circuit (10;19) comprises a) a flip-flop (134,174), b) associated gates (131 to 133;171 to 173) for receiving an access request and inhibiting the next request from the processor (1;2), c) a register (138;178), and d) associated gates (135 to 137;175 to 177) for receiving data and address request from the processor (1;2) and supplying them to the priority identifying circuit (11).

Claim 7

Apparatus according to any of Claims 3 to 5, characterized in that the priority identifying circuit (11) comprises a) a priority encoder (112), b) an inverter (113), c) a decoder (114), d) a multiplexor (115), and e) a flip-flop (116).

Claim 8

Apparatus according to any of Claims 2 to 6, charac- . terized in that the control circuit (23) comprises a) a flip-flop (231), b) a shift register (232), c) a flip-flop (233), and d) an AND gate (234).

Claim 9

Apparatus according to Claim 7, characterized in that the encoder (112) comprises a) inverters (1120 to 1131), b) AND gates (1132 to 1145), and c) OR gates (1146 to 1148).

Claim 10

Apparatus according to Claim 7 or 8, characterized in that the decoder (114) comprises a) inverters (1149 to 1156) and b) AND gates (1157 to 1166), and c) functions to decode the coded output of the encoder (112).

Claim 11

Apparatus according to any of Claims 6 to 9, characterized in that the multiplexer (115) comprises a) inverters (1167 to 1173,1183), b) AND gates (1174 to 1181), and c) a NAND gate (1182), whereby in response to a selection command from the encoder (112), the multiplexer (115) selects one of the data given from the circuits (10) and (19).