EP0077008A2 — Interface apparatus in a data processing system

Claim 1

Independent Claim 396 words

In a data processing system which includes first and second processors (70 and 31), a memory (30) adapted to be used by said processors for containing information to be shared by the procesors, and bus means (60, 110, 90) for interconnecting the first and second processors and memory to enable communications therebetween, said bus means being of the type which has no hardware interlock capability which is usable by each of said processors to selectively prevent the other of said processors from accessing at least a portion of said memory, the improvement comprising: the first and second processors (70 and 31) being adapted to employ a portion of said memory as a communications region (30A) accessible by both of said processors, so that all commands and responses can be transmitted from one of said processors to another of said processors through such portion of memory; the communications region of memory including a pair of ring buffers (30J and 80E); a first one of said ring buffers (30D) buffering the transmission of messages issued by the first processor (70) and a second one of said ring buffers (30E) buffering the reception of messages transmitted by the second processor (31); each of said ring buffers including a plurality of memory locations (e.g., 132, 134, 136 and 138) adapted to receive from the associated transmitting said processor a descriptor signifying another location in said memory; for said first ring buffer, the location signified by such descriptor being a location containing a message for transmission to the second processor; for said second ring buffer, the location signified by such descriptor beings a location for holding a message from the second processor; and the first and second processors (70 and 31) further being adapted to control access to said communications region (30k) such that information written therein by one of said processors may not be read twice by the other processor and a location where information is to be written by one of the processors may not be read by the other processor before said information has been written, so that race conditions are prevented from developing across said bus means and messages are transmitted from said ring buffers in the same sequence as that in which they are issued by the processors, while each of the processors is permitted to operate at its own rate, independent of the other processor.

Claim 2

Dependent Claim 396 words

In a data processing system which includes first and second processors (70 and 31), a memory (30) adapted to be used by said processors for containing information to be shared by the procesors, and bus means (60, 110, 90) for interconnecting the first and second processors and memory to enable communications therebetween, said bus means being of the type which has no hardware interlock capability which is usable by each of said processors to selectively prevent the other of said processors from accessing at least a portion of said memory, the improvement comprising: the first and second processors (70 and 31) being adapted to employ a portion of said memory as a communications region (30A) accessible by both of said processors, so that all commands and responses can be transmitted from one of said processors to another of said processors through such portion of memory; the communications region of memory including a pair of ring buffers (30J and 80E); a first one of said ring buffers (30D) buffering the transmission of messages issued by the first processor (70) and a second one of said ring buffers (30E) buffering the reception of messages transmitted by the second processor (31); each of said ring buffers including a plurality of memory locations (e.g., 132, 134, 136 and 138) adapted to receive from the associated transmitting said processor a descriptor signifying another location in said memory; for said first ring buffer, the location signified by such descriptor being a location containing a message for transmission to the second processor; for said second ring buffer, the location signified by such descriptor beings a location for holding a message from the second processor; and the first and second processors (70 and 31) further being adapted to control access to said communications region (30k) such that information written therein by one of said processors may not be read twice by the other processor and a location where information is to be written by one of the processors may not be read by the other processor before said information has been written, so that race conditions are prevented from developing across said bus means and messages are transmitted from said ring buffers in the same sequence as that in which they are issued by the processors, while each of the processors is permitted to operate at its own rate, independent of the other processor.

Claim 3

Dependent Claim 52 words

The apparatus of claim 1 wherein said ring buffers are adapted to permit the first processor to send a plurality of commands in sequence to the second processor via the bus means, and to permit the second processor to send responses to those commands to the first processor via the bus means.

Claim 4

Dependent Claim 56 words

The apparatus of claim 1 or claim 2 wherein the first processor (70) is a host computer's (2A) central processor, the second processor (31) is a processor in a controller (2B) for a secondary storage device (40), and the bus means includes an input/output bus (50) for interconnecting said host computer with said secondary storage device.

Claim 5

Dependent Claim 218 words

The apparatus of claim 3 wherein there is associated with each ring buffer entry a byte of at least one bit, termed the ownership byte (Fig. 38, 133, 135, 137, 139; Fig. 8, 278) , whose state indicates the status of that entry; 3 for each entry of the first ring buffer (30D), the first processor (70) being adapted to place such entry's ownership byte in a predetermined first state when a descriptor is written into said entry, and the second processor (31) being adapted to cause the state of the ownership byte to change when such descriptor is read from said entry; for each entry of the second ring buffer (30E), the second processor (31) being adapted to place such entry's ownership byte in a predetermined first state when a descriptor is written into said entry, and the first processor (70) being adapted to cause the state of the ownership byte to change when such descriptor is read from said entry; the first and second processors being adapted to read ring buffer entries in sequence and to read each ring buffer entry only when the ownership byte of said entry is in said predeternined first state, whereby an entry may not be read twice and an entry may not be read before a descriptor is written thereto.

Claim 6

Dependent Claim 27 words

The apparatus of claim 3 wherein the controller (28) further includes pointer means (32, 34) for keeping track of the current first and second ring buffer entries.

Claim 7

Dependent Claim 58 words

The apparatus of claim 3 further including means for reducing the generation of processor interrupt requests to the first one of said processors in the sending of commands thereby and responses thereto, such that interrupt requests to said processor are generated substantially only when an empty ring buffer becomes not-empty and when a full ring buffer becomes not-full.

Claim 8

Dependent Claim 38 words

The apparatus of claim 6 wherein the size of each ring buffer is communicated by said first one of the processors to the other of said processors at the time of initializin 3 a communications path between them.

Claim 9

Dependent Claim 236 words

The apparatus of claim 7 wherein the processors (70, 31) communicate by sending message packets to each other, and further inclu3ing: the first ring buffer (30D) being adapted to hold up to M commands to be executed; an input/output device class driver (3) associated with the first processor (70) for sending commands to and receiving responses from an input/output device (40); the second processor (31) being adapted to provide to the class driver (3) in its first response packet the number M of commands of a predetermined length which said buffer can hold; the class driver being adapted to maintain a credit account having a credit account balance indicative of the number of commands the buffer can accept at any instant; the credit account balance initially being set to equal M and being decremented by one each time the class driver issues a command and being incremented by the value; the second processor further being adapted to provide to the class driver, with each response packet, a credit value (Fig. 9, 288) representing the number of commands executed to evoke the response; the class driver incrementing the credit account balance by said credit value; and the first processsor and class driver being adapted so as not to issue any commands when the credit account balance is zero and further being adapted to issue only commands which are immediately executed when the credit account balance is one.

Claim 10

Dependent Claim 20 words

The apparatus of claim 4 wherein said ownership byte (278) is the most significant bit in each descriptor (260, 264).

Claim 11

Dependent Claim 374 words

In a data processing system which includes first and second processors (70 and 31), a memory (30) adapted to be used by said processors, and bus means (50, 110, 90) for interconnecting the first and second processors and memory to enable communications therebetween, said bus means being of the type which has no hardware interlock capability which is usable by each of said processors to selectively prevent the other of said processors from accessing at least a portion of said memory, the improvement comprising: at least a portion (80A) of said memory (30) being adapted to serve as a communications region accessible by both of said processors all commands and responses being transmitted fromf one processor to the other through such portion of memory; means (278) for controlling access to information in said communications region whereby information written therein by one of said processors may not be read twice by the other processor and wherein a location where information is to be written by one of the processors may not be read by the other processor before said information has been written; the communications region of memory including a pair of ring buffers (80D, 80E); a first one of said ring buffers (30D) being adapted to buffer the transmission of messages issued by the first processor and a second one of said ring buffers (30E) being adapted to buffer the reception of messages transmitted by the second processor; each of said ring buffers including a plurality of memory locations (e.g., Fig. 3B, 132, 134, 136, 138) adapted to receive from an associated one of said processors a descriptor (260, 264) signifying another location in said memory; for said first ring buffer, the location signified by such descriptor being a location containing a message for transmission to the second processor; and for said second ring buffer, the location signified by such descriptor being a location for holding a message from the second processor, so that race conditions are prevented from developin 3 across said bus means and messages are transmitted from said ring buffers in the same sequence as that in which they are issued by the processors, while each of the processors is permitted to operate at its own rate, independent.of the other processor.

Claim 12

Dependent Claim 374 words

In a data processing system which includes first and second processors (70 and 31), a memory (30) adapted to be used by said processors, and bus means (50, 110, 90) for interconnecting the first and second processors and memory to enable communications therebetween, said bus means being of the type which has no hardware interlock capability which is usable by each of said processors to selectively prevent the other of said processors from accessing at least a portion of said memory, the improvement comprising: at least a portion (80A) of said memory (30) being adapted to serve as a communications region accessible by both of said processors all commands and responses being transmitted fromf one processor to the other through such portion of memory; means (278) for controlling access to information in said communications region whereby information written therein by one of said processors may not be read twice by the other processor and wherein a location where information is to be written by one of the processors may not be read by the other processor before said information has been written; the communications region of memory including a pair of ring buffers (80D, 80E); a first one of said ring buffers (30D) being adapted to buffer the transmission of messages issued by the first processor and a second one of said ring buffers (30E) being adapted to buffer the reception of messages transmitted by the second processor; each of said ring buffers including a plurality of memory locations (e.g., Fig. 3B, 132, 134, 136, 138) adapted to receive from an associated one of said processors a descriptor (260, 264) signifying another location in said memory; for said first ring buffer, the location signified by such descriptor being a location containing a message for transmission to the second processor; and for said second ring buffer, the location signified by such descriptor being a location for holding a message from the second processor, so that race conditions are prevented from developin 3 across said bus means and messages are transmitted from said ring buffers in the same sequence as that in which they are issued by the processors, while each of the processors is permitted to operate at its own rate, independent.of the other processor.

Claim 13

Dependent Claim 53 words

ll. The apparatus of claim 10 wherein said ring buffers are adapted to permit the first processor to send a plurality of commands in sequence to the second processor via the bus means, and to permit the second processor to send responses to those commands to the first processor via the bus means.

Claim 14

Dependent Claim 56 words

The apparatus of claim 10 or claim 11 wherein the first processor is a host computer's (2A) central processor (70), the second processor is a processor (31) in a controller (2B) for la secondary storage device (40), and the bus means includes an input/output bus (50) for interconnecting said host computer with said secondary storage device.

Claim 15

Dependent Claim 218 words

The apparatus of claim 12 wherein there is associated with each ring buffer entry a byte of at least one bit, termed the ownership byte (Fig. 38, 133, 135, 137, 139; Fig. 8, 273), whose state indicates the status of that entry; for each entry of the first ring buffer (30D), the first processor (70) being adapted to place such entry's ownership byte in a predetermined first state when a descriptor (260, 264) is written into said entry, and the second processor (31) being adapted to cause the state of the ownership byte to change when such descriptor is read from said ent.ry; for each entry of the second ring buffer (80E), the second processor (31) being adapted to place such entry's ownership byte in a predetermined first state when a descriptor is written into said entry, and the first processor (70) being adapted to cause the state of the ownership byte to change when such descriptor is read from said entry; the first and second processors being adapted to read ring buffer entries in sequence and to read each ring buffer entry only when the ownership byte of said entry is in said predetermined first state, whereby an entry may not be read twice and an entry may not be read before a descriptor is written thereto.

Claim 16

Dependent Claim 26 words

The apparatus of claim 12 wherein the controller further includes pointer means (32, 34) for keeping track of the current first and second ring buffer entries.

Claim 17

Dependent Claim 59 words

The apparatus of claim 12 further including means for reducing the generation of processor interrupt requests to the first one of said processors in the sending of commands thereby and responses thereto, such that interrupt requests to said processor are generated substantially only when an empty ring buffer becomes non-empty and when a full ring buffer becomes not full.

Claim 18

Dependent Claim 37 words

The apparatus of claim 15 wherein the size of each ring buffer is communicated by said first one of the processors to the other of said processors at the time of initializing the communications path between them.

Claim 19

Dependent Claim 225 words

The apparatus of claim 16 wherein the processors communicate by sending message packets to each other, and further including: a buffer associated with the second processor for holding up to M commands to be executed; an input/output device class driver associated with the first processor for sending commands to and receiving responses from an input/output device; the second processor being adapted to provide to the class driver in its first response packet the number M of commands of a predetermined length which said buffer can hold; the class driver being adapted to maintain a credit account having a credit account balance indicative of the number of commands the buffer can accept at any instant; the credit account balance initially being set to equal M and being decremented by one each time the class driver issues a command and being incremented by the value; the second processor further being adapted to provide to the class driver, with each response packet, a credit value representing the number of commands executed to evoke the response; the class driver incrementing the.credit account balance by said credit value; and the first processsor and class driver being adapted so as not to' issue any commands when the credit account balance is zero and further being adapted to issue only commands which are immediately executed when the credit account balance is one.

Claim 20

Dependent Claim 17 words

The apparatus of claim 13 wherein said ownership byta is the most significant bit in each descriptor.

Claim 21

Dependent Claim 145 words

In a data processing system which includes a host processor (70), mass storage means (40), mass storage control means (30) for controlling the operation of the mass storage means, and bus means (60) for interconnecting the host processor and the mass storage control means to enable communication therebetween, a register (38) connected to the bus means and through which various information may be transmitted between the host processor and the mass storage control means, and said register having multiple locations for storing bit values, a method of initializing operation of the data processing system comprising the steps of: (a) confirming the proper operation of the register locations by writing thereto and reading therefrom (326, 350, 372, 374, 386, 398, 405); and (b) the host processor sending to the mass storage means, via the register, values for predetermined parameters characteristic of the host (336, 366, 380).

Claim 22

Dependent Claim 145 words

In a data processing system which includes a host processor (70), mass storage means (40), mass storage control means (30) for controlling the operation of the mass storage means, and bus means (60) for interconnecting the host processor and the mass storage control means to enable communication therebetween, a register (38) connected to the bus means and through which various information may be transmitted between the host processor and the mass storage control means, and said register having multiple locations for storing bit values, a method of initializing operation of the data processing system comprising the steps of: (a) confirming the proper operation of the register locations by writing thereto and reading therefrom (326, 350, 372, 374, 386, 398, 405); and (b) the host processor sending to the mass storage means, via the register, values for predetermined parameters characteristic of the host (336, 366, 380).

Claim 23

Dependent Claim 32 words

The method of claim 19 further including the step of: (c) the mass storage means sending to the host, via the register, data and error information relating to the initialization process (398).

Claim 24

Dependent Claim 201 words

In a data processing system which includes a host processor, mass storage means, mass storage control means for controlling the operation of the mass storage means, and bus means for interconnecting the host processor and the mass storage control means to enable communication therebetween, a register connected to the bus means and through which various information may be transmitted between the host processor and the mass storage control means, and said register having multiple locations for storing bit values, a method of initializing operation of the data processing system comprising the steps of: (a) the host processor writing to said register values for predetermined parameters characteristic of the host; (b) the mass storage control means reading said register to obtain therefrom said parameter values; (c) the mass storage control means writing to said register at least a portion of said parameter values, in different locations than had been used by the host in writing said parameter values to the register; (d) the host.reading said register and comparing the parameter values written to the register by the mass storage control means with the parameter values written to the register by the host, to confirm proper operation of bit locations in the register.

Claim 25

Dependent Claim 201 words

In a data processing system which includes a host processor, mass storage means, mass storage control means for controlling the operation of the mass storage means, and bus means for interconnecting the host processor and the mass storage control means to enable communication therebetween, a register connected to the bus means and through which various information may be transmitted between the host processor and the mass storage control means, and said register having multiple locations for storing bit values, a method of initializing operation of the data processing system comprising the steps of: (a) the host processor writing to said register values for predetermined parameters characteristic of the host; (b) the mass storage control means reading said register to obtain therefrom said parameter values; (c) the mass storage control means writing to said register at least a portion of said parameter values, in different locations than had been used by the host in writing said parameter values to the register; (d) the host.reading said register and comparing the parameter values written to the register by the mass storage control means with the parameter values written to the register by the host, to confirm proper operation of bit locations in the register.

Claim 26

Dependent Claim 27 words

The method of claim 21 wherein the register is in the input/output page of host address space but physically is part of the mass storage control means.

Claim 27

Dependent Claim 37 words

The method of claim 21 wherein said writing and reading steps are performed a sufficient number of times and with a sufficient number of parameters so as to confirm proper operation of all,bit locations in the register.

Interface apparatus in a data processing system

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