Semiconductor memory device having a programming circuit

Claim 2

1 . A semiconductor device comprising memory means (4 6 ) which is connected to a first power supply terminal at one end and of which the impedance is set at one of two levels in a nonvolatile state, and output circuit means connected to the other end of said memory means (46), characterized in that said output circuit means comprises switching means (50) connected between the other end of said memory means (46) and a second power supply terminal, and control means (52, 54, 56, 58) which is provided with delay means (58) and controls the conduction of said switching means (50) according to the voltage at the other terminal of said memory means (46).

Claim 3

A semiconductor device according to claim 1, characterized in that said switching means consists of a MOSFET (50), and said control means is formed of an odd number of series-connected inverters (52, 54, 56) which invert the voltage at the junction between said memory means (46) and said.MOSFET (50) and supply the inverted signal to the gate of said MOSFET (50), and a capacitor (58) connected between the ground and any output terminal of said inverters (52, 54, 56).

Claim 4

A semiconductor device according to claim 1, characterized in that said output circuit means comprises pulse generator means (84) for supplying a pulse to a control terminal of said switching means' (50) to render it conductive, and latch means (80) for latching the level of the other terminal of said memory means (46) upon receipt of an output pulse from said pulse generator means (84).

Claim 5

A semiconductor device according to claim 3, characterized in that said latch means (80) comprises a flip-flop circuit (92) including a pair of NOR gates, and having a first input terminal connected to the junction between said memory means (46) and said switching means (50) and a second input terminal connected to the output terminal of said pulse generator means (84), and a MOSFET (94), connected between at least one of said power supply terminals and the first input terminal of said flip-flop circuit (92), having a gate supplied with an output signal from said flip-flop circuit (92).

Claim 6

A semiconductor device according to claim 3, characterized in that said latch means (80) comprises a first MOSFET (102) and an even number of inverters (104, 106) connected in series to the junction between said memory means (46) and said switching means (50), and a second MOSFET (108) connected in parallel to said even number of inverters (104, 106), and an output pulse from said pulse generator means (84) is supplied to the gate of the first MOSFET (102) and in an inverted state to the gate of the second MOSFET (108).

Claim 7

A semiconductor device according to claim 1, characterized in that said memory means (46) consists of a polysilicon fuse and a switch (48) connected between the junction of said polysilicon fuse (46) and said switching means (50) and the second power supply terminal, said polysilicon fuse (46) being blown when the switch (48) is rendered conductive.

Claim 8

A semiconductor device comprising flip-flop circuit means (128, 168) having first and second output terminals, memory means (130, 140, 170) of which the impodance is set at one of two levels in a nonvolatile state, characterized in that there is provided a first capacitance means (132, 172) which is connected to the first output terminal of said flip-flop circuit means (128, 16o) through said memory means (130, 140, 170) and a second capacitance means (134, 176) which is connected to the second output terminal of said flip-flop circuit means (128, 168) and has a different capacitance from the first capacitance means (132, 172).

Claim 9

A semiconductor device comprising flip-flop circuit means (128, 168) having first and second output terminals, memory means (130, 140, 170) of which the impodance is set at one of two levels in a nonvolatile state, characterized in that there is provided a first capacitance means (132, 172) which is connected to the first output terminal of said flip-flop circuit means (128, 16o) through said memory means (130, 140, 170) and a second capacitance means (134, 176) which is connected to the second output terminal of said flip-flop circuit means (128, 168) and has a different capacitance from the first capacitance means (132, 172).

Claim 10

A semiconductor device according to claim 7, characterized in that said flip-flop circuit means (168) consists of CMOS circuits.

Claim 11

A semiconductor device according to claim 7, characterized in that said memory means is formed of a polysilicon fuse (130, 170) blown by laser beams.

Claim 12

A semiconductor device according to claim 7, characterized in that said memory means is formed of a polysilicon resistor (140) whose resistivity is reduced by laser annealing.

Claim 13

ll. A semiconductor device according to claim 7, characterized in that said second capacitance means (134) is connected ; the second output terminal of the flip-flop circuit means (128) through memory means (150) of which the impedance is set at one of two levels in a nonvolatile state.

Claim 14

A semiconductor memory device comprising normal memory cells (22), spare memory cells (24), normal decoder means (32) for selecting one of said normal memory cells (22) according to an address signal, spare decoder means (36) for selecting one of said spare memory cells (24) and inhibiting the selection of said normal decoder means (32), programming means (34) for permitting the selection of said spare decoder means (36), characterized in that said programming means (34) includes memory means (46) of which the impedance is set at one of two levels in a nonvolatile state and switching means (50), both means being connected in series beween first and second power supply terminals, control means (52, 54, 56, 58) which comprises delay means (58) and controls the conduction of said switching means (50) according to the voltage at the junction between said memory means and (46) said switching means (50), and selector means (60, 62) which supplies an address signal or an inverted address signal to said spare decoder means (36) according to the voltage level at the junction between said memory means (46) and said switching means (50).

Claim 15

A semiconductor memory device comprising normal memory cells (22), spare memory cells (24), normal decoder means (32) for selecting one of said normal memory cells (22) according to an address signal, spare decoder means (36) for selecting one of said spare memory cells (24) and inhibiting the selection of said normal decoder means (32), programming means (34) for permitting the selection of said spare decoder means (36), characterized in that said programming means (34) includes memory means (46) of which the impedance is set at one of two levels in a nonvolatile state and switching means (50), both means being connected in series beween first and second power supply terminals, control means (52, 54, 56, 58) which comprises delay means (58) and controls the conduction of said switching means (50) according to the voltage at the junction between said memory means and (46) said switching means (50), and selector means (60, 62) which supplies an address signal or an inverted address signal to said spare decoder means (36) according to the voltage level at the junction between said memory means (46) and said switching means (50).

Claim 16

A semiconductor memory device according to claim 12, characterized in that said switching means consists of a MOSFET (50), and said control means is formed of an odd number of series-connected inverters (52, 54, 56) which invert the voltage at the junction between said memory means (46) and said MOSFET (50) and supply the inverted signal to the gate of the MOSFET (50), and a capacitor (58) connected between the ground and any output terminal of said odd number of inverters (52, 54, 56).

Claim 17

A semiconductor memory device according to claim 12, characterized in that said control means comprises pulse generator means (84) which supplies a pulse to a control terminal of said switching means (50) to render it conductive, and latch means (80) for latching the level at the other terminal of said memory means (46) upon receipt of an output pulse from said pulse generator means (84).

Claim 18

A semiconductor memory device according to claim 14, characterized in that said latch means (80) comprises a flip-flop circuit (92) including a pair of NOR gates, and having a first input terminal connected to the junction between said memory means (46) and said switching means (50) and a second input terminal connected to the output terminal of said pulse generator means (84), and a MOSFET (94) connected between at least one of said power supply terminals and the first input terminal of said flip-flop circuit (92), having a gate supplied with an output signal from said flip-flop circuit (92).

Claim 19

A semiconductor memory device according to claim 14, characterized in that said latch means (80) comprises a first MOSFET (102) and an even number of inverters (104, 106) connected in series to the junction between said memory means (46) and said switching means (50), and a second MOSFET (108) connected in parallel to said even number of inverters (104, 106), and an output pulse from said pulse generator means (84) is supplied to the gate of said first MOSFET (102) and an inverted output pulse from said pulse generator means (84) to the gate of said second MOSFET (108).

Claim 20

A semiconductor memory device according to claim 12, characterized in that said memory means (46) comprises a polysilicon fuse and a switch (48) connected between the junction of the polysilicon fuse (46) and said switching means (50) and said second power supply terminal, said polysilicon fuse (46) being blown when the switch (48) is rendered conductive.

Claim 21

A semiconductor memroy device according to claim 12, characterized in that said programming means (34) includes memory means (130, 140, 170) of which the impedance is set at one of two levels in a nonvolatile state, flip-flop circuit means (128, 168) having first and second output terminals, first capacitance means (132, 172) connected to the first output terminal of said flip-flop circuit means (128, 168) through said memory means (130, 140, 170), and second capacitor means (134, 176) connected to the second output terminal of said flip-flop circuit means (128, 168) and has a different capacitance from said first capacitance means (132, 172).

Claim 22

A semiconductor memory device according to claim 18, characterized in that said flip-flop circuit means (168) consists of CMOS circuits.

Claim 23

A semiconductor memory device according to claim 18, characterized in that said memory means is formed of a polysilicon fuse (130, 170) blown by laser beams.

Claim 24

A semiconductor memory device according to claim 18, characterized in that said memory means is formed of a polysilicon resistor (140) whose resistivity is reduced by laser annealing.

Claim 25

A semiconductor memory device according to claim 18, characterized in that said second capacitance means (134) is connected to the second output terminal of said flip-flop circuit means (128) through memory means (150) of which the impedance is set at one of two levels in a nonvolatile state.

Claim 26

A semiconductor memory device according to claim 12, characterized in that said programming means (34) includes a plurality of first series circuits each comprising a first fuse (200-1 to 200-N) and first channel MOSFET (198-1 to 198-N) whose gate is supplied with an address signal, a plurality of second series circuits each comprising a second fuse (204-1 to 204-N) and first channel MOSFET (202-1 to 202-N) whose gate is supplied with an inverted address signal, a plurality of first and second series circuits being connected in parallel between one power supply terminal and an output terminal, a plurality of third series circuits each comprising a third fuse (190-1 to 190-N) and second channel MOSFET (188-1 to 188-N) whose gate is supplied with an address signal, and a plurality of fourth series circuits each comprising a fourth fuse (196-1 to 196-N) and a second channel MOSFET (194-1 to 194-N) whose gate is supplied with an inverted address signal and each connected to a respective third series circuit in parallel, one of said first and third fuses and said second and fourth fuses being blown in accordance with an address signal representing a defective normal memory cell.