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EP0100943A2
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Hierarchical memory system
Assignee: International Business Machines Corp
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Filing: 1983-07-22
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Granted: —
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Expires: 2003-07-22
Abstract
Abstract A hierarchical memory system is disclosed comprising at least one dual-ported memory level (9, 19), each port having access to a separate bidirectional data bus (1, 2). The port (9) facing the higher memory levels is equipped with a pair of data buffers (5, 6) having a bit width equal to the bit width of a single row of cells in the storage array (4) contained within the dual-ported level. One buffer (output) is loaded in one cycle from the array. The other buffer (input) is emptied in one cycle into the array. Both buffers interact with the higher memory level independently of the transferring of data through the other of the dual ports. Thus, contention for the use of bus facilities and contention for memory cycles are greatly reduced in the transferring of data between the memory levels.
Inventors
- 👤 Russell William Lavallee
- 👤 Philip Meade Ryan
- 👤 Vincent Francis Sollitto, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 07:47
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0859
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
143 words
Hierarchical memory system having a plurality of memory levels, characterized in that one or more of the memory levels (N-1, N, N+l) have dual data ports (9, 19), one of which is equipped with one or more data buffers (5, 6), that each of the memory levels with dual data ports has a data storage array (4) with a bit width equal to the bit width of the buffers, that an internal data bus (3) of bit width equal to the bit width of the array and the buffers is provided for connecting the array to the buffers and to the other (19) of the dual data ports, and that first and second bidirectional data buses (2, 1) are provided for interconnecting the buffered port (9) to a higher memory level and for interconnecting the other port (19) to a lower level, respectively.
Claim 2
Dependent Claim
143 words
Hierarchical memory system having a plurality of memory levels, characterized in that one or more of the memory levels (N-1, N, N+l) have dual data ports (9, 19), one of which is equipped with one or more data buffers (5, 6), that each of the memory levels with dual data ports has a data storage array (4) with a bit width equal to the bit width of the buffers, that an internal data bus (3) of bit width equal to the bit width of the array and the buffers is provided for connecting the array to the buffers and to the other (19) of the dual data ports, and that first and second bidirectional data buses (2, 1) are provided for interconnecting the buffered port (9) to a higher memory level and for interconnecting the other port (19) to a lower level, respectively.
Claim 3
Dependent Claim
65 words
The hierarchical memory system of claim 1, characterized in that the buffered port comprises a first selector (7) and first driver and receiver means (9) for interconnecting the first bidirectional bus (2) to the data buffer (5) via the first selector (7), the bit width of the first driver and receiver means and of the first selector being less than that of the buffer (5).
Claim 4
Dependent Claim
38 words
The hierarchical memory system of claim 2, characterized in that the bit width of the buffer (5) is a multiple of the bit width of the first driver and receiver means (9) and of the first selector (7).
Claim 5
Dependent Claim
53 words
The hierarchical memory system of any one of the claims 1 - 3, characterized in that the buffered port is equipped with two data buffers (5, 7) of equal bit width, and that no more than one of the buffers is operatively connected to the internal data bus (3) at a given time.
Claim 6
Dependent Claim
43 words
The hierarchical memory system of claim 4, characterized in that neither of the two data buffers (5, 7) are operatively connected to the internal data bus (3) when the internal data bus is in communication with the other of the dual data ports.
Claim 7
Dependent Claim
44 words
The hierarchical memory system of claim 4 or 5, characterized in that one of the buffers (5, 7) is in communication with the first data bus (2) at the same time that the array (4) is in communication with the second data bus (1).
Claim 8
Dependent Claim
41 words
The hierarchical memory system of any one of the claims 1 - 3, characterized in that the buffer is in communication with the first data bus (2) independent of the communication of the array (4) with the second data bus (1).
Claim 9
Dependent Claim
34 words
The hierarchical memory system of any one of the claims 1 - 7, characterized in that the higher memory level (N+1) is the main memory and the lower level (N) is the cache memory.
Claim 10
Dependent Claim
50 words
The hierarchical memory system of any of the claims 1 - 8, characterized in that the buffered port comprises a second selector (8) for interconnecting the second bidirectional bus (2) to the internal bus (3), the bit width of the second selector being less than that of the internal bus.
Claim 11
Dependent Claim
29 words
The hierarchical memory system of claim 9, characterized in that the bit width of the first selector (7) is equal to the bit width of the second selector (8).
References Cited (Backward Citations)
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