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EP0101107A2
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EP
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Method of testing a semiconductor memory array
Assignee: Motorola Solutions Inc
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Filing: 1983-07-11
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Granted: —
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Expires: 2003-07-11
Abstract
Abstract This invention relates to a method of testing an array 15 of rows 8, 9 and columns 10, 11 floating gate avalanche injection MOS memory elements. In the method a stress test is carried out by applying a stressing potential simultaneously to a plurality of rows 8, 9 or to a plurality of columns 10, 11 of the array 15. The invention is particularly useful in the testing of EPROMS.
Inventors
- 👤 Michel Bron
- 👤 Anil Gercekci
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 15:20
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C16/00; G11C16/02; G11C16/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
88 words
A method of testing an array of rows and columns of floating gate avalanche injection MOS memory elements, each element including a transistor having a source electrode, a drain electrode, a control gate electrode and a floating gate, the transistors in a row having their gate electrodes electrically connected together and the transistors in a column having their drain electrodes electrically connected together, the method including the steps of applying a stressing potential simultaneously to a plurality of rows or to a plurality of columns of the array.
Claim 2
Independent Claim
88 words
A method of testing an array of rows and columns of floating gate avalanche injection MOS memory elements, each element including a transistor having a source electrode, a drain electrode, a control gate electrode and a floating gate, the transistors in a row having their gate electrodes electrically connected together and the transistors in a column having their drain electrodes electrically connected together, the method including the steps of applying a stressing potential simultaneously to a plurality of rows or to a plurality of columns of the array.
Claim 3
Dependent Claim
21 words
A method as claimed in claim 1 wherein the stressing potential is applied simultaneously to all the rows of the array.
Claim 4
Dependent Claim
21 words
A method as claimed in claim 1 wherein the stressing potential is applied simultaneously to all the columns of the array.
Claim 5
Dependent Claim
61 words
An array of rows and columns of floating gate avalanche injection MOS memory elements each element comprising a transistor having a source electrode, a drain electrode, a control gate electrode and a floating gate, the array including means for applying a stressing potential for test purposes simultaneously to a plurality of rows or to a plurality of columns of the array.
Claim 6
Dependent Claim
61 words
An array of rows and columns of floating gate avalanche injection MOS memory elements each element comprising a transistor having a source electrode, a drain electrode, a control gate electrode and a floating gate, the array including means for applying a stressing potential for test purposes simultaneously to a plurality of rows or to a plurality of columns of the array.
Claim 7
Dependent Claim
30 words
An array as claimed in claim 4, wherein the means for applying a stressing potential includes means for applying a stressing potential simultaneously to all the rows of the array.
Claim 8
Dependent Claim
30 words
An array as claimed in claim 4, wherein the means for applying a stressing potential includes means for applying a stressing potential simultaneously to all the columns of the array.
Claim 9
Dependent Claim
51 words
An array as claimed in claim 4 or 5 or 6, wherein the array includes decoding means for enabling a programming potential to be applied to a selected row or column of the array the means for applying a stressing potential including means for overriding the action of the decoding means.
Claim 10
Dependent Claim
40 words
An array as claimed in claim 7, wherein the means for overriding the action of the decoding means is operative to apply the programming potential and the stressing potential simultaneously to a plurality of rows or columns of the array.
Claim 11
Dependent Claim
32 words
An array as claimed in claim 8, wherein the means for overriding the action of the decoding means comprises gating means for enabling application of the programming potential as the stressing potential.
Claim 12
Dependent Claim
19 words
An array as claimed in claim 9, wherein the gating means is responsive to a stress test electing signal.
References Cited (Backward Citations)
No citation records indexed.
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