Patent EP0107355A2 successfully refreshed from Google Patents.
EP0107355A2
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CMIS circuit device
Assignee: Fujitsu Ltd
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Filing: 1983-09-23
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Granted: —
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Expires: 2003-09-23
Abstract
Abstract A CMIS circuit device such as an IC chip of a semiconductor memory device which is made selectable by using at least two chip-select signals (CS,, CS 2 ) having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state and a chip-unselected state upon receiving the above-mentioned chip-select signals. The chip-select control circuit comprises a CMIS inverter means (IV,) for inverting one of the chip-select signals (CS 2 ) and a CMIS logic gate means (lV 2 ) for receiving an output signal (a) of the CMIS) inverter means and the other chip select signal or signals (CS 1 ) and for outputting an internal chip-select control signal (CS). The CMIS inverter means (IV 1 ) comprises a CMIS inverter (Q 20 , Q 21 ) and one or more control transistors (Q 19 ) which receive the other chip-select signal or signals (CS 1 ) at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.
Inventors
- 👤 Keizo Aoyama
- 👤 Takahiko Yamauchi
- 👤 Teruo Seki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 12:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016; G; G11; G11C; G11C8/00; G11C8/18; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
178 words
A CMIS circuit device the state of which is controlled by at least two input signals (CS 1 , CS2) and which is made selectable on receiving input signals at least two of which have opposite polarities, the CMIS circuit device having a chip-select control circuit for establishing a chip-selected state and a chip-unselected state in accordance with the received input signals, the chip-select control circuit comprising CMIS inverter means (IV 1 ) for inverting one of the input signals (CS 2 ), and CMIS logic gate means ( IV2 ) for receiving an output signal (a) of the CMIS inverter means (IV 1 ) and the other input signal or signals (CS I ) and for outputting an internal chip-select control signal (CS), wherein the CMIS inverter means (IV 1 ) comprises a CMIS inverter (Q20, Q21) and one or more control transistors (Q 19 ) receiving the other input signal or signals (CS 1 ) at the gates thereof and which are inserted in series between a.power terminal of the CMIS inverter and a power source.
Claim 2
Dependent Claim
178 words
A CMIS circuit device the state of which is controlled by at least two input signals (CS 1 , CS2) and which is made selectable on receiving input signals at least two of which have opposite polarities, the CMIS circuit device having a chip-select control circuit for establishing a chip-selected state and a chip-unselected state in accordance with the received input signals, the chip-select control circuit comprising CMIS inverter means (IV 1 ) for inverting one of the input signals (CS 2 ), and CMIS logic gate means ( IV2 ) for receiving an output signal (a) of the CMIS inverter means (IV 1 ) and the other input signal or signals (CS I ) and for outputting an internal chip-select control signal (CS), wherein the CMIS inverter means (IV 1 ) comprises a CMIS inverter (Q20, Q21) and one or more control transistors (Q 19 ) receiving the other input signal or signals (CS 1 ) at the gates thereof and which are inserted in series between a.power terminal of the CMIS inverter and a power source.
Claim 3
Dependent Claim
45 words
A CMIS circuit device according to claim 1, wherein the CMIS logic gate means (IV 2 ) comprises a NOR gate which receives the output signal (a) of the CMIS inverter means (IV 1 ) and the other input signal or signals (CS 1 ):
Claim 4
Dependent Claim
123 words
A CMIS circuit device according to claim 2, wherein the NOR gate comprises a plurality of series-connected transistors (Q 23' Q24) having a first conductivity type connected in series with a plurality of parallel-connected transistors (Q 25 ,Q 26 ) having a second conducitivity type, the gate of one of the series-connected transistors (Q 23 ) and the gate of one of the parallel-connected transistors (Q 25 ) receiving the output signal (a) of the C MIS inverter means (IV 1 ), each of the other input signals (CS 1 ) being fed to gates of a respective pair of the remaining transistors each pair including one of the series-connected transistors (Q 24 ) and one of the parallel-connected transistors (Q 26 ).
Claim 5
Dependent Claim
45 words
A CMIS circuit device according to claim 1, wherein the CMIS logic gate means (IV 2 ) comprises a NAND gate which receives the output signal (a) of the CMIS inverter means (IV 1 ) and the other input signal or signals (CS 1 ).
Claim 6
Dependent Claim
124 words
A CMIS circuit device according to claim 4, wherein the NAND gate comprises a plurality of parallel-connected transistors (Q 19 ,Q 10 ) having a first conductivity type connected in series with a plurality of series-connected transistors (Q 11' Q 12 ) having a second conductivity type, the gate of one of the parallel-connected transistors (Qg) and the gate of one of the series-connected transistors (Q 11 ) receiving the output signal (a) of the C MIS inverter means (IV 1 ), and the or each of the other input signals (CS 1 ) being fed to gates of respective pairsof the remaining transistors each pair including one of the parallel-connected transistors (Q 10 ) and one of the series-connected transistors (Q 12 )
Claim 7
Dependent Claim
48 words
A CMIS circuit device according to any of the preceding claims, wherein the or each control transistor (Q 19 ) is connected between a transistor (Q20) of the CMIS inverter (IV 1 ) having the same conductivity type as that of the control transistor, and a power source.
Claim 8
Dependent Claim
64 words
A CMIS circuit device according to any of the preceding claims, further comprising one or more input circuits (IPC), each of which is controlled by the internal chip-select control signal (CS) and each of which causes an input signal (IN) applied to an internal circuit of the CMIS circuit device to assume a voltage level near the power supply voltage or the ground level.
Claim 9
Dependent Claim
118 words
A CMIS circuit device of claim 8, wherein each of the input circuits (IPC) comprises a plurality of series-connected transistors (Q 5 ,Q 6 ) having a first conductivity type connected in series with a plurality of parallel-connected transistors (Q 7 ,Q B ) having a second conductivity type, the gate of one of the series-connected transistors EQ 6 ) and the gate of one of the parallel-connected transistors (Q 7 ) receiving an input signal (IN) of the CMIS circuit device and the gate of the other series-connected transistor (Q 5 ) and the gate of the other parallel-connected transistor (Q ) receiving the internal chip-select control signal ( CS ) output from the chip-select control circuit.
Claim 10
Dependent Claim
33 words
A CMIS circuit device according to any of the preceding claims, wherein the control circuit further comprises additional CMIS inverter means (IV 3 ) for inverting the internal chip select control signal (CS).
References Cited (Backward Citations)
No citation records indexed.
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