Patent US1380518A successfully refreshed from Google Patents.
Patent EP0109298A2 successfully refreshed from Google Patents.
EP0109298A2
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Computer memory
Assignee: EMC Corp
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Filing: 1983-11-14
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Granted: —
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Expires: 2003-11-14
Abstract
Abstract Selection logic (1) responds to 7 out of 22 address bits on a bus (19) to select the module by providing a signal SETRAS, delayed by a signal PRECHG if the same row is address twice in succession. SETRAS generates a row address strobe RAS, a recognition signal ANYRAS and, after a delay (11), a column address signal CAS 16 address bits held in a latch (3) are multiplexed 8 bits at a time a multiplexer (4) and, in synchronism with RAS and CAS select locations in even and odd memory arrays (16 and 17). Two more address bits and selection logic (20) select between four planes in each array. The memory controller responds to the recognition signal ANYRAS to provide an output strobe DOUTSTB - DOUTLTCH to enter both read out words into latches (7, 8). Either (or both in sequence) of further signals from the controller DRVDOUTO, cause one or both words to be read out in sequence to the data bus (18).
Inventors
- 👤 Michael Ziegler
- 👤 Peter G. Marshall
- 👤 David L. Whipple
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 15:41
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0607; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
293 words
A memory module for storing digital information, characterised by the combination of means (19) for receiving an address signal from a digital signal source, comparison means (1) for comparing a module address in the address signal with stored information and operative, in response to a coincidence between the stored information and the module address, to provide a row address strobe signal (RAS) and a recognition signal (ANYRAS) for return to the digital signal source, first delay means (11) responsive to the row address strobe signal (RAS) for providing a column address strobe signal (CAS), first and second pluralities of ordered sets (16 and 17) of memory elements, means (3, 4, 15) responsive to the address signal for providing row and column selection signals selecting corresponding sets of elements in both of the said pluralities, these means including multiplexer means (4) providing the row and column selection signals sequentially in correspondence with strobe (RAS) and column address strobe (CAS) signals, output latch means (7, 8) for concurrently storing two information words from the selected sets of memory elements of the two pluralities respectively, the latch means being responsive to a word selection signal (DRVDOUTO,l) the digital signal source for selectively providing the source with one of the information words or with both words in sequence, means (5, 6) for receiving a data word from the digital signal source, second delay means (12) responsive to one of two write selection signals (LDDINO,l) for selectively providing a write enabling signal (WEEVEN, WEODD) to one of the two pluralities of memory elements (16 or 17), the selected set of memory elements of the selected plurality being responsive to the row address strobe (RAS), column address strobe (CAS) and write enabling signals for storing the received data word.
Claim 2
Dependent Claim
293 words
A memory module for storing digital information, characterised by the combination of means (19) for receiving an address signal from a digital signal source, comparison means (1) for comparing a module address in the address signal with stored information and operative, in response to a coincidence between the stored information and the module address, to provide a row address strobe signal (RAS) and a recognition signal (ANYRAS) for return to the digital signal source, first delay means (11) responsive to the row address strobe signal (RAS) for providing a column address strobe signal (CAS), first and second pluralities of ordered sets (16 and 17) of memory elements, means (3, 4, 15) responsive to the address signal for providing row and column selection signals selecting corresponding sets of elements in both of the said pluralities, these means including multiplexer means (4) providing the row and column selection signals sequentially in correspondence with strobe (RAS) and column address strobe (CAS) signals, output latch means (7, 8) for concurrently storing two information words from the selected sets of memory elements of the two pluralities respectively, the latch means being responsive to a word selection signal (DRVDOUTO,l) the digital signal source for selectively providing the source with one of the information words or with both words in sequence, means (5, 6) for receiving a data word from the digital signal source, second delay means (12) responsive to one of two write selection signals (LDDINO,l) for selectively providing a write enabling signal (WEEVEN, WEODD) to one of the two pluralities of memory elements (16 or 17), the selected set of memory elements of the selected plurality being responsive to the row address strobe (RAS), column address strobe (CAS) and write enabling signals for storing the received data word.
Claim 3
Dependent Claim
36 words
A memory module according to claim 1, characterised in that the output latch means (7, 8) provides the selected information word or words to the digital data source continuously until the word selection signal (DRVDOUTO,1) terminates.
Claim 4
Dependent Claim
127 words
A memory module according to claim 1 or 2, characterised in that the output latch means (7, 8) accepts words from the memory elements in response only to a strobe signal (DOUTSTB) from the digital signal source and thereafter maintains the words read from the memory elements independent of further changes in the output of the memory elements, whereby following the storage of information words in the latch means a new module address may be provided to the module and the words in the latch means may be read out during the time necessary for the first delay means (11) to address the memory elements selected by the new address, so that four consecutive words may be read from the memory module without addressing delays between words.
Claim 5
Dependent Claim
61 words
A memory module according to claim 1, 2 or 3, characterised in that themeans for receiving the address signal comprises an address latch (3) responsive to an address strobe signal (ADRSTB) from the digital signal source for storing the address of the selected elements for as long as an address latch signal (ADRLTCH) provided from the address strobe signal is asserted.
Claim 6
Dependent Claim
83 words
A memory module according to any of claims 1 to 4, characterised in that the first delay means (11) provides a delayed multiplexer control signal (CASADR) before providing the column address strobe signal (CAS), and in that the multiplexer means (4) is responsive to this control signal for connecting the memory elements to the column selection signals after the application of the rwo selection signals and the row address strobe signal (RAS) and before the application of the column address strobe signal (CAS).
Claim 7
Dependent Claim
160 words
A memory module according to any of claims 1 to 5 in combination with a digital signal source (23 or 100), an interconnecting data bus (18) and an interconnecting address bus (19), characterised by interconnecting control lines carrying the following signals from the source to the module (101) ADDRESS STROBE (ADRSTB) DATA OUT STROBE (DOUTSTB) DRIVE DATA OUT ODD (DRVOUT1) DRIVE DATA OUT EVEN (DRVDOUTO) and the recognition signal (ANYRAS) from the module to the source, in that the module responds to the address signal and ADDRESS STROBE to provide the row address strobe signal (RAS) and the recognition signal (ANYRAS) and in that the source responds to the recognition signal to provide in sequence the DATA OUT STROBE signal and either or both of the DRIVE DATA out signals to read words into the output latch means (7, 8) and the read out a selected one of these words, or both words in sequence, to the data bus (18).
Claim 8
Dependent Claim
59 words
A memory module and digital signal source according to claim 6, characterised by a further line carrying a PRECHARGE signal (PRECHRG) from the source (23 or 100) to the module (101) for delaying the generation of the row address strobe signal (RAS) and the recognition signal (ANYRAS) when the same row of the module is addressed twice in succession.
References Cited (Backward Citations)
No citation records indexed.
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