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EP0121798A2
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Dynamic type semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1984-03-09
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Granted: —
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Expires: 2004-03-09
Abstract
Abstract A dynamic type semiconductor memory device is disclosed, which comprises an n-type semiconductor layer (14), at least one memory cell having a capacitor (10) for storing charges of an amount corresponding to a logic value and a first transistor (12) having source and drain regions (18, 20) formed in the surface area of the p-type semiconductor layer and for transferring charges to and from the capacitor (10), a first drive circuit (WL) for applying a voltage to the gate of the first transistor (12) through a word line (WL), a second drive circuit for selectively applying a voltage of one of first and second levels (VS, VC) through a bit line (BL) and the first transistor (12) to the capacitor (10), and a bias circuit for applying a voltage to the substrate (10). The first transistor (12) of the memory device is a p-channel transistor formed in the n-type semiconductor layer (16) which is formed in the surface area of a p-type semiconductor layer (14). The bias circuit includes a charge pump section (41) for setting the potential of the substrate at a third level (VB) lower than the first voltage (VS).
Inventors
- 👤 Tohru Furuyama
- 👤 Yukimasa Uchida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 16:16
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/408; G11C11/4087
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
215 words
A dynamic type semiconductor memory device comprising a semiconductor body including a first layer (16) of one conductivity type; at least one memory cell having a first MOS transistor (12) whose source and drain regions (18, 20) of an opposite conductivity type are formed in the surface area of said first layer (16) and a first capacitor (10) connected to a bit line (BL) through a current path of said first MOS transistor (12); first means for biasing said semiconductor body; second means for controlling a conduction state of said first MOS transistor (12) through a word line (WL); and third means for selectively setting the potential of said bit line (BL) at one of a first level and a second level higher than said first level, characterized in that said semiconductor body further includes a second layer (14) of the opposite conductivity type formed in contact with said first layer (16), said first means has bias means for supplying an output voltage to said second layer (14) to apply a reverse bias voltage between said first and second layers, said second means has a drive circuit which sets the potential of said word line (WL) to in accordance with the output voltage from said bias means to render said first MOS transistor (12) conductive.
Claim 2
Dependent Claim
215 words
A dynamic type semiconductor memory device comprising a semiconductor body including a first layer (16) of one conductivity type; at least one memory cell having a first MOS transistor (12) whose source and drain regions (18, 20) of an opposite conductivity type are formed in the surface area of said first layer (16) and a first capacitor (10) connected to a bit line (BL) through a current path of said first MOS transistor (12); first means for biasing said semiconductor body; second means for controlling a conduction state of said first MOS transistor (12) through a word line (WL); and third means for selectively setting the potential of said bit line (BL) at one of a first level and a second level higher than said first level, characterized in that said semiconductor body further includes a second layer (14) of the opposite conductivity type formed in contact with said first layer (16), said first means has bias means for supplying an output voltage to said second layer (14) to apply a reverse bias voltage between said first and second layers, said second means has a drive circuit which sets the potential of said word line (WL) to in accordance with the output voltage from said bias means to render said first MOS transistor (12) conductive.
Claim 3
Dependent Claim
84 words
A dynamic type semiconductor memory device according to claim 1, characterized in that said first layer (16) is of n-type, said second layer (14) is of p-type, said bias means is provided for applying a voltage of a third level (VB) lower than said first level to said second layer (14), and said drive circuit is provided for changing the potential of said word line (WL) from said second level (VC) to said third level (VB) to render said first MOS transistor (12) conductive.
Claim 4
Dependent Claim
36 words
A dynamic type semiconductor memory device according to claim 2, characerized in that said bias means has a charge pamp circuit 41) which sets the potential of said second layer (14) to said third level (VB).
Claim 5
Dependent Claim
109 words
A dynamic type semiconductor memory device according to claim 3, characterized in that said charge pump circuit (41) includes an output terminal (VBB) connected to said second layer (14), second and third MOS transistors (46, 48) whose gates are respectively connected to their drains and whose current paths are connected in series between said output terminal (VBB) and a reference potential terminal, a pulse oscillator (42), and a second capacitor (44) connected to said pulse oscillator (42), said second capacitor (44) being charged and discharged respectively through said second and third transistors (46, 48) in response to the rising and falling of the pulse from said pulse oscillator (42).
Claim 6
Dependent Claim
65 words
A dynamic type semiconductor memory device according to claim 4, characterized in that said drive circuit includes a fourth transistor (60) having a current path connected between said word line (WL) and said output terminal (VBB) of said charge pump circuit (41), and CMOS transistors (56, 58) which control a conduction state of said fourth MOS transistor (60) in response to a control signal (W).
Claim 7
Dependent Claim
92 words
A dynamic type semiconductor memory device according to claim 5, characterized in that said drive circuit further includes a voltage generator (35) which ganerates a voltage of said second level (VC) for a predetermined period in response to said control signal (W), one end of the current path of said CMOS transistors (56, 58) is connected to the output terminal of said voltage generator (55), and the cther end of the current path of said CMOS transistors (56, 58) is connected to said output terminal (VBB) cf said charge pump circuit (41).
Claim 8
Dependent Claim
74 words
A dynamic type semiconductor memory device according to claim 1, characterized in that said first layer is of n-type, said second layer is of p-type, said bias means is provided for applying a voltage of a third level lower than said first layers, and said drive circuit is provided for changing the potential of said word line (WL) from said second level to said third level to render said first MOS transistor (12) conductive.
Claim 9
Dependent Claim
34 words
A dynamic type semiconductor memory device according to claim 7, characterized in that said bias means has a charge pump circuit (41) which sets the potential of said second layer to said third level.
Claim 10
Dependent Claim
107 words
A dynamic type semiconductor memory device according to claim 8, characterized in that said charge pump circuit (41) includes an output terminal (VBB) connected to said second layer, second and third MOS transistors (46, 48) whose gate are respectively connected to their drains and whose current paths are connected in series between said output terminal (VBB) and a reference potential terminal, a pulse oscillator (42), and a second capacitor (44) connected to said pulse oscillator (42), said second capacitor (44) being charges and discharges respectively through said second and third transistors (46, 48) in response to the rising and falling of pulse from said pulse oscillator (42).
Claim 11
Dependent Claim
64 words
A dynamic type semiconductor memory device according to claim 9, characterized in that said drive circuit includes a fourth transistor (60) having a current path connected between said word line (WL) and said output terminal (VBB) of said charge pump circuit (41), and CMOS transistors (56, 58) which control a conduction state of said fourth MOS transistor in response to a control signal (W).
Claim 12
Dependent Claim
90 words
A dynamic type semiconductor memory device according to claim 10, characterized in that said drive circuit further includes a voltage generator (55) which generates a voltage of said second level for a predetermined period in response to said control signal (W), one end of the current path of said CMOS transistors (56, 58) is connected to the output terminal of said voltage generator (55), and the other end of current path of said CMOS transistors (56, 58) is connected to said output terminal (VBB) of said charge pump circuit (41).
Claim 13
Dependent Claim
75 words
A dynamic type semiconductor memory device according to claim 1, characterized in that said first layer is of p-type, said second layer is of n-type, said bias means is provided for a voltage of third level higher than said-second level to said said second layer, and said drive circuit is.provided for changing the potential of said word line (WL) from said first level to said third level to render said first MOS transistor (12) conductive.
Claim 14
Dependent Claim
33 words
A dynamic type semiconductor memory device according to claim 12, characterized in that said bias means has a charge pamp circuit which sets the potential of said first layer to said third level.
Claim 15
Dependent Claim
96 words
A dynamic type semiconductor memory device according to claim 13, characterized in that said charge pump circuit includes an output terminal connected to said second layer, second and third MOS transistors whose gates are respectively connected to their drains and whose current paths are connected in series between said output terminal and a reference potential terminal, a pulse oscillator, and a second capacitor connected to said pulse oscillator, said second capacitor being charged and discharged respectively through said second and third transistors in response to the rising and falling of the pulse from said pulse oscillator.
Claim 16
Dependent Claim
63 words
A dynamic type semiconductor memory device according to claim 14, characterized in that said drive circuit includes a fourth transistor (60) having a current path connected between said word line (WL) and said output terminal of said charge pump circuit, and CMOS transistors (56, 58) which control a conduction state of said fourth MOS transistor (60) in response to a control signal (W).
Claim 17
Dependent Claim
89 words
A dynamic type semiconductor memory device according to claim 15, characterized in that said drive circuit further includes a voltage generator (55) which generates a voltage of said second level for a predetermined period in response to said control signal (W), one end of the current path of said-CMOS transistors (56, 58) is connected to the output terminal of said voltage generator (55), and the other end of the current path of said CMOS transistors (56, 58) is connected to said output terminal of said charge pump circuit (41).
Claim 18
Dependent Claim
78 words
A dynamic type semiconductor memory device according to claim 1, characterized in that said first layer is of p-type, said second layer is of n-type, said bias means is provided for applying a voltage of a third level higher than said second level to said second layer, and said drive circuit is provided for changing the potential of said word line (WL) from said first level to said third level to render said first MOS transistor (12) conductive.
Claim 19
Dependent Claim
33 words
A dynamic type semiconductor memory device according to claim 17, characterized in that said bias means has a charge pump circuit which sets the potential of said first layer to said third level.
Claim 20
Dependent Claim
96 words
A dynamic type semiconductor memory device according to claim 18, characterized in that said charge pump circuit includes an output terminal connected to said second layer (16), second and third MOS transistors whose gates are respectively connected to their drains and whose current paths are connected in series between said output terminal and a reference potential terminal, a pulse oscillator, and a second capacitor connected to said pulse oscillator, said second capacitor being charged and discharged respectively through said second and third transistors in response to the rising and falling of pulse from said pulse oscillator.
Claim 21
Dependent Claim
63 words
A dynamic type semiconductor memory device according to claim 19, characterized in that said drive circuit includes a fourth transistor (60) having a current path connected between said word line (WL) and said cutput terminal of said charge pump circuit, and CMOS transistors (56, 58) which control a conduction state of said fourth MOS transistor (60) in response to a control signal (W).
References Cited (Backward Citations)
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