Semiconducter ROM device and method for manufacturing the same

Claim 1

A read only memory semiconductor device characterized by comprising: a pair of regions (12, 13) of a first conductivity type (N + ) formed in a semiconductor substrate (11) of a second conductivity type (P) opposite to said first conductivity type, the pair of regions individually forming drain and source regions of a MOS transistor; a first insulation film (21) for gate insulation formed on said substrate; a first conductive layer for a gate electrode (14) formed on said gate insulation film; a second insulation film (22, 23) formed on said gate electrode; a second conductive layer (16) containing an impurity of said first conductivity formed on one of said pair of regions, the second conductivity layer extending onto said second insulation film which is on said gate electrode; and a third conductive layer (18) formed on said second conductive layer.

Claim 5

A method of manufacturing a read only memory semiconductor device characterized by comprising the steps of: forming a field insulation region (20) in a semiconductor substrate (11) of a first conductivity type (P) to form a region for an element isolated from other region of the substrate; forming a first insulation film (21) for gate insulation on the element region; forming a first conductive layer for gate electrode (14) on said gate insulation film; doping an impurity of a second conductivity type (N) opposite to said first conductivity type into said element region, using as a mask said field insulation region and gate electrode to form a pair of semiconductor regions (12, 13) of said second conductivity type; forming a second insulation film (22) on the entire major surface of the semiconductor structure; forming a contact hole (15), in said second insulation film, leading to one of said pair of semiconductor regions; forming a second conductive layer (16) of an impurity of said second conductivity type with a predetermined pattern on the entire major surface of the semiconductor structure, the second conductive layer contacting said one of the pair of semiconductor region and extending onto that part of said second insulation film which is on said gate electrode; forming a third insulation film (24) on the entire major surface of the semiconductor structure; forming a contact hole (17), in said third insulation film, leading to said second conductive layer according to the information to be stored; and forming a third conductive layer (18) with a predetermined pattern on the entire major surface of semiconductor structure.

Claim 6

A method of manufacturing a read only memory semiconductor device characterized by comprising the steps of: forming a field insulation region (20) in a semiconductor substrate (11) of a first conductivity type (P) to form a region for an element isolated from other region of the substrate; forming a first insulation film (21) for gate insulation on the element region; forming a first conductive layer for gate electrode (14) on said gate insulation film; doping an impurity of a second conductivity type (N) opposite to said first conductivity type into said element region, using as a mask said field insulation region and gate electrode to form a pair of semiconductor regions (12, 13) of said second conductivity type; forming a second insulation film (22) on the entire major surface of the semiconductor structure; forming a contact hole (15), in said second insulation film, leading to one of said pair of semiconductor regions; forming a second conductive layer (16) of an impurity of said second conductivity type with a predetermined pattern on the entire major surface of the semiconductor structure, the second conductive layer contacting said one of the pair of semiconductor region and extending onto that part of said second insulation film which is on said gate electrode; forming a third insulation film (24) on the entire major surface of the semiconductor structure; forming a contact hole (17), in said third insulation film, leading to said second conductive layer according to the information to be stored; and forming a third conductive layer (18) with a predetermined pattern on the entire major surface of semiconductor structure.