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EP0125855A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Buffer-storage control system

Assignee: Fujitsu Ltd
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Filing: 1984-05-04
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Granted: —
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Expires: 2004-05-04
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Abstract

Abstract A buffer-storage control system used in a pipeline data processor comprises a memory system having a two-level hierarchical structure composed of a main storage (3, Figure 1) and a buffer storage (8). The buffer storage (8) has a tag portion (21) and a data portion (22), each portion being composed of a plurality of ways. In the buffer-storage control sytem, the tag portion (21) and the data portion (22) can be independently accessed and the data portion (22) is so constituted for every way that it is possible to select one of a plurality of address passes and to select an address for a read access and an address for a write access for every way, thereby simultaneously effecting a read operation and write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same way.

Inventors

  • 👤 Hirosada Tone

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 12:08
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0864

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 141 words
A buffer-storage control system in a data processor comprising a main storage (MSU) and a buffer storage (8) which has a tag portion (21) and a data portion (22), each portion composed of a plurality of ways, characterised in that the buffer-storage control system is so constituted that the tag portion (21) and the data portion (22) can be independently accessed, and that the data portion (22) is so constituted for every way that it is possible to select one of a plurality of address paths and to select an address for a read access and an address for a write access for every way, thereby simultaneously effecting a read operation and a write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same way.
Claim 2
Dependent Claim 141 words
A buffer-storage control system in a data processor comprising a main storage (MSU) and a buffer storage (8) which has a tag portion (21) and a data portion (22), each portion composed of a plurality of ways, characterised in that the buffer-storage control system is so constituted that the tag portion (21) and the data portion (22) can be independently accessed, and that the data portion (22) is so constituted for every way that it is possible to select one of a plurality of address paths and to select an address for a read access and an address for a write access for every way, thereby simultaneously effecting a read operation and a write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same way.
Claim 3
Dependent Claim 77 words
A buffer-storage control system according to claim 1, comprising comparators (23-0 ... 23-F) for every way, each of which comparators compares an address for access operation and an address stored in the corresponding way, and a way number register (25) for memorizing a number of a way corresponding to the comparator which outputs a coincidence signal, the output of the way number register (25) being used for selecting the address in every-way of the data portion (22).
Claim 4
Dependent Claim 75 words
A buffer-storage control system according to.claim.2, further comprising selectors (28-O ... 28-F), each of which is associated with a respective way of the data portion (22) and each of which selects one of two addresses input thereto from an effective address register (9) and an operand address register (11) of a storage control unit (7) of the control system, the selectors being controlled on the basis of the output of the way number register (25).
Claim 5
Dependent Claim 52 words
A buffer-storage control system according to claim 3, further comprising an OR circuit (26) which receives signals of valid bits from the ways of the tag portion (21), and a gate circuit (29) which passes the output of the way number register (25) in accordance with the output of the OR circuit.
Claim 6
Dependent Claim 47 words
A buffer-storage control system according to any of claims 2 to 4, further comprising a way-coincidence detecting circuit (13) which detects coincidences between the way number memorized in the way number register (25) and the number of the way memorizing address which corresponds to an input address.

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