Electronic padlock for a subscriber telephone line

Claim 2

1) Electronic padlock for subscriber's telephone line, characterized in that it comprises a circuital arrangement providing the presence in combination of the following characteristic elements: - a sensor (SS), connected to the telephone line, adapted to render available a first signal (S) whose level indicates the condition of the line itself; - a logic unit (UL) adapted to store a predetermined combination of di gits, further adapted to rebuild the digits dialled by the subscriber on the ground of the exam of the level of the first signal (S), and also arranged to generate a second signal (R) when it detects the pre sence of a predetermined relationship between the combination of digits stored therein and the digits dialled by subscriber; - a threshold circuit (Z1, R1) connected in parallel with the telephone terminal; - an inhibiting electric branch (T1), adapted to be connected in parallel with the telephone terminal (TL) upon command by the said logic unit (UL) and of the said threshold circuit (Zl, R1), the branch being of such an impedance as to result crossend during the openings of the line, by a current of predetermined entity; - a supply unit (UA) adapted to extract energy fran the telephone line and further adapted to render available a direct voltage of supply (VDD) of the said logic unit (UL).

Claim 3

2) A circuital arrangement as claimed in claim 1, characterized in that the said threshold circuit consists of a first Zener diode (Zl) whose anode results to be connected to a first resistance.(R1).

Claim 4

3) A circuital arrangement as claimed in claim 1, characterized in that the said inhibiting electric branch (T1) provides the presence in combi nation of the following characteristic elements: - a first transistor (Q1) whose gate electrode results to be connected to the anode of the first Zener diode (Zl) via a second resistance (R2), whose source electrode results to be connected to a wire of the line, and whose drain electrode results to be connected to the other wire of the line via a third resistance (R5); - a second transistor (Q3) whose drain electrode results to be connected to the gate electrode of the first transistor (Ql), whose source electrode is connected to the source electrode of the first transistor (Q1) and whose gate electrode receives the said second signal (R); - a second Zener diode (Z2) connected between the base and the emitter of the first transistor (Ql).

Claim 5

4) A circuital arrangement as claimed in claim 1, characterized in that the said sensor (SS) consists of a voltage sensor and provides the presence in combination of the following characteristic elements: - a third transistor (Q2) whose gate electrode is connected to the anode of the first Zener diode (Z1) via a fourth resistance (R3), whose source electrode is connected to a wire of the line and whose drain electrode receives the voltage (VDD) supplied by the said supply unit (UA) via a fifth resistance (R4); - a third Zener diode (Z3) connected between the base and the emitter of the third transistor (Q2).

Claim 6

5) A circuital arrangement as claimed in claim 1, characterized in that the said supply unit (UA) provides the presence in combination of the following characteristic elements: - a capacitor (C) whose primary plate is connected to the wire of the line and whose secondary plate is connected to the cathode of a first diode (Dl); -.a fourth transistor (Q4) whose collector is connected to the anode of the first diode (M) via a sixth resistance (R6) and a second diode (D2), whose emitter is connected to the other wire of the line and whose base is connected to the collector of the first transistor via a seventh resistance (R7); - on eighth resistance (R8) connected between the cathode of the second diode (D2) and emitter of the fourth transistor (04); - a fourth Zener diode (Z4) connected between the anode of the first diode (D1) and the first plate of said capacitor (C); - an electric branch, comprising a cell (P) and a third diode placed in series with one another, connected in parallel with the capacitor (C).

Claim 7

6) A circuital arrangement as claimed in claim 1 characterized in that the said sensor (SS) consists of a current sensor and provides the presence in combination of the following characteristic elements: - a nineth resistance (R9) connected in series with one of the wires of the telephone line; - a fifth transistor (Q2') whose base is connected to the first reophore of the nineth resistance (R9) via a tenth resistance (RIO) the emitter is connected to the second reophore of the nineth resistance (R9) and the collector connected to the voltage (VDD) furnished by the supply unit (UA) via an eleventh resistance (R11); - an inverter (I) connected to the collector of the fifth transistor (Q2'); - a fourth diode (D4) connected in parallel with the eighth resistance (R8).

Claim 8

7) A Circuital arrangement as claimed in claims 2, 4 and 5, characterized in that in the said threshold circuit the first resistance (R1) is in the form of a twelfth and of a thirteenth resistance (R1' and Rl") connected to a respective electrode of the first Zener diode (Z1), in that the collector of the fourth transistor (Q4) is connected to the cathode of the first Zener diode (Z1) via an electric branch comprising, in series with one another, a fifth diode (D5) and a fourteenth resistance (R12), in that in the said voltage sensor (SS) the second transistor (Q2) provides the base connected to the anode of the first Zener diode (Z1), the emitter connected to the base of the first transistor - (Q1) and the collector connected to the supply voltage (VDD) via the said fifth resistance (R4).

Claim 9

8) A circuital arrangement as claimed in claim 1 characterized in that the said logic unit (UL) provides the presence in combination of the fol lowing characteristic elements: - signal regeneration means (MRS) whose input is adapted to receive the said first signal (S); - combination storing means (MMC) connected to the output of the signal regeneration means (MRS); - digit identification means (MRC) connected to the output of the digit storing means (MMC).

Claim 10

9) A circuital arrangement as claimed in claim 8 characterized in that the said signal regeneration means (MRS) provide the presence in canbi- nation of the following characteristic elements: - a reset unit (AZ) adapted to activate its own output with a delay, longer than the period of the ring signal, with respect to the activation of the said first signal (S); - an impulse shaper (FI) adapted to activate its own output in response to each activation of the said first signal (S); - a digit shaper (FC) adapted to activate its own output in response to each sequence of activations of the said first signal (S); - a delay circuit (CR) adapted to activate its own output in response to each sequence of activation of the said first signal (S), at an instant preceeding the activation of the output of the digit shaper (FC).

Claim 11

10) A circuital arrangement as claimed in claim 8 characterized in that the said combination storing means (MMC) provide the presence in combination of the following characteristic elements: - an impulse counter (CI) connected to the output of said impulse shaper (FI); - a digit counter (CF) connected to the output of the digit shaper (FC); - a random access memory (RAM) whose address input is connected to the output of the digit counter (CF) and whose data input is connected to the output of the impulse counter (CI); - a comparison circuit (CC) whose first input is connected to the output of the random access memory (RAM) and whose second input is connected to the output of the impulse counter (CI); - an addressable register (AL) whose address input is connected to the output of the digit counter (CF) and whose data input is connected to the output of the comparison circuit (CC); - a first commutator (C1) adapted to allow the application of a polarity to an input of the random access memory (RAM).

Claim 12

11) A circuital arrangement as claimed in claim 7, characterized in that the said combination identification means (MRC) provide the presence in combination of the following characteristic elements: - a first logic product unit (Al) whose inputs are connected to the out puts of the addressable register (AL); - a first logic sum unit (01) whose input is adapted to receive the output of the first logic product unit (Al) and the output (r) of the reset unit (A Z ); - a first bistable circuit (FF1) whose enabling inputs are connected to the output of the first logic sum unit (01) and whose timing input is connected to the output of the digit shaper (FC); - a second logic sum unit (02) whose first input is connected to the output of the first bistable circuit (FF1) and whose second input is connected to the output (r) of the reset unit (AZ); - a second bistable circuit (FF2) whose data input is applied to a fixed polarity and whose timing input is connected to the first output of the addressable register (AL); - a second commutator (C2) adapted to connect the output of the first bistable circuit (FF1) or to the reversed output of the second bista ble circuit (FF2) or to the ground potential to the first input of the said second logic sum unit (02); - a third commutator (C3) adapted to connect the reset input of the first bistable circuit (FF1) to the ground potential or to the output (r) of the said reset unit (AZ).

Claim 13

12) A circuital arrangement as claimed in claim 8, characterized in that the said combination storing means (MMC) provide the presence in combination of the following characteristic elements: - a digit counter (CF) whose input is connected to the output if the di git shaper (FC); - k impulse counters (CI1,... ,CIk), k being the number of digits provided in the combination, whose enabling inputs are connected to a respective output of the digit counter (CF) and whose counting inputs are connected to the output of the impulse shaper (FI).

Claim 14

13) A circuital arrangement as claimed in claim 1, characterized in that the said logic unit consists of a microcomputer.

Claim 15

14) A circuital arrangement as claimed in claim 1 characterized in that the said logic unit (UL) consists of the said reset unit (AZ).

Claim 16

15) A circuital arrangement as claimed in claim 1, characterized in that it results to be housed inside a metallic structure electrically connected to one of the line wires.

Claim 17

16) A circuital arrangement as claimed in claim 1, characterized in that it results to be connected to the telephone line via a bridge of diodes (PD) which is connected in parallel with a device designed to protect against overvoltages (PS).