Patent EP0145606A2 successfully refreshed from Google Patents.
EP0145606A2
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EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1984-12-12
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Granted: —
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Expires: 2004-12-12
Abstract
Abstract @ A semiconductor memory device, such as a MOS dynamic RAM device, having memory cells each comprising a transfer gate transistor (10) and a capacitor (11). The capacitor (11) is a so-called groove-type capacitor and has a conductive layer (18) formed on an insulation film (17) attached to the inside surface of a groove (16) formed on a semiconductor substrate (12). The conductive layer (18) is electrically coupled to the source (14) of the transfer gate transistor (10). The capacitance of the capacitor (11) is formed between the conductive layer (18) and a second conductive layer (20) formed on the conductive layer (18) via an insulation film (19), and/or between the conductive layer (18) and the semiconductor substrate (12).
Inventors
- 👤 Yoshihiro Takemae
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 16:01
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; H10B12/01; H10B12/02; H10B12/03; H10B12/038
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
75 words
A semiconductor memory device provided with memory cells each comprising: a transfer gate transistor having a drain, a source, and a gate formed on the channel region between said drain and source via a gate insulation film; and a capacitor having a conductive layer formed on an insulation film attached to the inside surface of a groove formed on a substrate, said conductive layer being electrically coupled to the source of said transfer gate transistor.
Claim 2
Dependent Claim
75 words
A semiconductor memory device provided with memory cells each comprising: a transfer gate transistor having a drain, a source, and a gate formed on the channel region between said drain and source via a gate insulation film; and a capacitor having a conductive layer formed on an insulation film attached to the inside surface of a groove formed on a substrate, said conductive layer being electrically coupled to the source of said transfer gate transistor.
Claim 3
Dependent Claim
41 words
A semiconductor memory device according to claim 1, wherein said capacitor further comprises anotehr conductive layer formed on said conductive layer via an insulation film, the capacitance of said capacitor being formed between said conductive layer and said another conductive layer.
Claim 4
Dependent Claim
50 words
A semiconductor memory device according to claim 1, wherein said capacitor further comprises a high impurity concentration layer formed under said groove and having the same conductivity type as that of said substrate, the capacitance of said capacitor being formed between said conductive layer and said high impurity concentration layer.
Claim 5
Dependent Claim
52 words
A semiconductor memory device according to claim 3, wherein said capacitor further comprises another conductive layer formed on said conductive layer via an insulation film the capacitance of said capacitor being formed between said conductive layer and said another conductive layre and between said conductive layer and said high impurity concentration layer.
Claim 6
Dependent Claim
20 words
A semiconductor memroy device according to claim 3, wherein said high density layer is seperately formed for each memory cell.
Claim 7
Dependent Claim
24 words
A semiconductor memory device according to claim 3, wherein said high impurity concentration layer is formed commonly to the grooves of adjoining memory cells.
Claim 8
Dependent Claim
27 words
A semiconductor memory device according to claim 2, wherein both said conductive layer and said another conductive layer extend over the gate of said transfer gate transistor.
Claim 9
Dependent Claim
27 words
A semiconductor memory device according to claim 4, wherein both said conductive layer and said another conductive layer extend over the gate of said transfer gate transistor.
Claim 10
Dependent Claim
54 words
A semiconductor memory device according to claim 1, wherein said transfer gate transistor and said capacitor are formed on a semiconductor layer which has a conductivity type opposite to that of said substrate and which is formed on said substrate, the PN junction formed by said semiconductor layer and said substrate being reversely biased.
Claim 11
Dependent Claim
21 words
A semiconductor memory device according to claim 9, wherein the groove of said capacitor reaches said substrate through said semiconductor layer.
Claim 12
Dependent Claim
39 words
A semiconductor memory device according to claim 9, wherein the groove of said capacitor exists within said semiconductor layer, and the depletion region formed along said PN junction is in contact with at least a part of said groove.
Claim 13
Dependent Claim
25 words
A semiconductor memory device according to claim 11, wherein said semiconductor layer is not formed in the area between the grooves of adjoining memory cells.
References Cited (Backward Citations)
No citation records indexed.
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