Semiconductor memory device having a redundancy circuit

Claim 2

A semiconductor memory device comprising: a random-access memory having at least one redundancy column for replacing a defective column; serial output means for reading in parallel and outputting serially data stored in said random-access memory; and redundancy means for replacing data of said defective column in data serially output from said serial output means with data of said redundancy column.

Claim 3

A semiconductor memory device as claimed in claim 1, wherein said redundancy means comprises: at least one read-only memory for storing an address corresponding to said defective column; at least one latch means for latching data read out from said redundancy column; at least one comparator for comparing an input column address with a defective column address and first for outputting a/coincidence signal when said input column address coincides with said defective column address; at least one counter being started by a producing second clock signal and for producing second a coincidence signal when a number held in said counter coincides with a column number indicating said defective column; and a multiplexer for replacing data of said defective column with data of said redundancy column when said second coincidence signal is input.

Claim 4

A semiconductor memory device as claimed in claim 1, wherein said redundancy means comprises: at least one read-only memory for storing an address corresponding to said defective column; at least one means for latching the data read out from said redundancy column; at least one comparator for comparing an input column address with a defective column address and for outputting a coincidence signal when said input column address coincides with said defective column address; a decoder for decoding said defective column address; a plurality of flip-flop circuits for turning ON corresponding gates based on said defective column address; and a data bus for replacing data of said defective column with said data of said redundancy column.

Claim 5

A semiconductor memory device as claimed in claim 1, 2, or 3 wherein said serial output means comprises a shift register group for shifting the data read out from said random-access memory in response to a clock signal.

Claim 6

A semiconductor memory device as claimed in claim 1 or 2, wherein said serial output means comprises: a plurality of flip-flop circuits for latching the data read out from said random-access memory; a plurality of gates for transferring the data latched in said flip-flop circuits a plurality of pointers for sequentially turning ON in response to a clock signal; and a shift data bus connected to said gates for outputting the data.

Claim 7

A semiconductor memory device as claimed in claim 5, further comprising: at least one redundancy flip-flop circuit for latching data read out from said redundancy column; and a redundancy data bus connected to said redundancy flip-flop circuit for outputting data latched in said redundancy flip-flop circuit.

Claim 8

A semiconductor memory device as claimed in claim 5, further comprising at least one redundancy flip-flop circuit for latching data read out from said redundancy column, said redundancy flip-flop circuit being connected to said shift data bus.

Claim 9

A semiconductor memory device as claimed in claim 5 or 7, wherein a start position of said pointer is operable to be arbitrarily selected by said clock signal.

Claim 10

A semiconductor memory device as claimed in claim 2 or 3, or any of claims 4 to 8 as appended to claim 2 or 3, wherein said at least one read-only memory is operable to be commonly used for a random access mode and a serial output mode.

Claim 11

A semiconductor memory device including: a random access memory having a redundancy column for replacing a defective column, if any, occurring in the random access memory; output means for reading out in parallel and outputting serially data stored in said random access memory; and redundancy means, for replacing data of the defective column with data of the redundancy column, comprising address storing means for storing an address corresponding to the defective column, detecting means for detecting selection of the address corresponding to the defective column, and replacing means for replacing data of the defective column read out by said output means by data of the redundancy column.

Claim 12

A semiconductor memory device including: a random access memory having a redundancy column for replacing a defective column, if any, occurring in the random access memory; output means for reading out in parallel and outputting serially data stored in said random access memory; and redundancy means, for replacing data of the defective column with data of the redundancy column, comprising address storing means for storing an address corresponding to the defective column, detecting means for detecting selection of the address corresponding to the defective column, and replacing means for replacing data of the defective column read out by said output means by data of the redundancy column.