Patent EP0176254A2 successfully refreshed from Google Patents.
EP0176254A2
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EP
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1985-08-27
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Granted: —
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Expires: 2005-08-27
Abstract
Abstract A dynamic random access memory has a semiconductive substrate (10) in which grooves (12) are formed such that each grooves has side walls and a bottom portion and which has a predetermined conductivity type. Each memory cell formed on the substrate has a transistor (14) and a capacitor (16) buried in the groove (12). The capacitor (16) is constituted by a first conductive layer (32) and a second conductive layer (36). The first conductive layer (32) is connected to a source region (20) of the transistor (14) and has a layer portion (32b) extending in the groove (12) along the side wall thereof. The second conductive layer (36) is insulated from the first conductive layer (32), buried in the groove (12) to oppose the first conductive layer (32) and allows the conductive layer (32) to store charge carriers in response to a voltage applied between the first and second conductive layers (32, 36). The second conductive layer (36) serves as a common electrode for all the memory capacitors (16) formed on the substrate (10).
Inventors
- 👤 Katsuhiko C/O Patent Division Hieda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 12:11
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/31; H10B12/01; H10B12/02; H10B12/03; H10D; H10D1/00; H10D1/60; H10D1/68; Y; Y10; Y10S; Y10S257/00; Y10S257/906
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
183 words
A semiconductor memory device comprising a semiconductive substrate (10) on which memory cells are formed, wherein said substrate (10) has a predetermined conductivity type and grooves (12) each of which has side walls and a bottom portion (44), and wherein each memory cell comprises a transistor (14) formed on said substrate (10) and a capacitor (16) buried in said groove (12), characterized in that said capacitor (16) comprises: a first conductive layer (32, 32') which is connected to a source region (20) of said transistor (14) and has a layer portion (32b) extending in said groove (12) along said side wall of said groove (12), and a second conductive layer (36) which is insulated from said first conductive layer (32, 32') and buried in said groove (12) to oppose said first conductive layer (32, 32') to allow said first conductive layer (32, 32') to store charge carriers in response to a voltage applied between said first and second conductive layers (32, 32'; 36), said second conductive layer (36) serving as a common electrode for all the memory capacitors formed on said substrate (10).
Claim 2
Dependent Claim
183 words
A semiconductor memory device comprising a semiconductive substrate (10) on which memory cells are formed, wherein said substrate (10) has a predetermined conductivity type and grooves (12) each of which has side walls and a bottom portion (44), and wherein each memory cell comprises a transistor (14) formed on said substrate (10) and a capacitor (16) buried in said groove (12), characterized in that said capacitor (16) comprises: a first conductive layer (32, 32') which is connected to a source region (20) of said transistor (14) and has a layer portion (32b) extending in said groove (12) along said side wall of said groove (12), and a second conductive layer (36) which is insulated from said first conductive layer (32, 32') and buried in said groove (12) to oppose said first conductive layer (32, 32') to allow said first conductive layer (32, 32') to store charge carriers in response to a voltage applied between said first and second conductive layers (32, 32'; 36), said second conductive layer (36) serving as a common electrode for all the memory capacitors formed on said substrate (10).
Claim 3
Dependent Claim
48 words
The device according to claim 1, characterized in that said grooves (12) are formed in a field area of said substrate (10) to define memory cell areas having surface portions, and that said transistor (16) is formed on each of the surface area portions of said memory cells.
Claim 4
Dependent Claim
77 words
The device according to claim 2, characterized in that said second conductive layer (36) serving as the common electrode extends at substantially a central portion of said groove (12) to be substantially perpendicular with respect to the substrate surface, and said first conductive layers (32, 32') serving as the capacitor electrodes have layer portions (32b) which extend substantially perpendicularly with respect to the substrate surface and oppose each other with said second conductive layer (36) sandwiched therebetween.
Claim 5
Dependent Claim
40 words
The device according to claim 3, characterized in that said first conductive layers (32, 32') serving as the capacitor electrodes of said neighbouring cells are formed to be shallower than said second conductive layer (36) serving as the common electrode.
Claim 6
Dependent Claim
36 words
The device according to claim 4, characterized by further comprising a semiconductive layer (46) formed in said substrate (10) to surround said groove (12) and having a conductivity type opposite to that of said substrate (10).
Claim 7
Dependent Claim
32 words
The device according to claim 5, characterized in that said semiconductive layer (46) comprises a semiconductive layer section (48) which is locally thick at the bottom portion (44) of said groove (12).
Claim 8
Dependent Claim
29 words
The device according to claim 6, characterized in that said first and second conductive layers (32, 32'; 36) are constituted by polycrystalline silicon films insulatively stacked with each other.
Claim 9
Dependent Claim
51 words
The device according to claim 1, characterized in that said grooves (12) are formed in the surface of said substrate (10) to have rectangular sections, and said first conductive layer (32, 32') is formed to have inverted L-shaped sections along an edge portion of the side wall of said groove (12).
Claim 10
Dependent Claim
51 words
The device according to claim 8, characterized in that said second conductive layer (36) is formed to have a T-shaped section in said groove (12), and comprises a layer component (36b) extending substantially parallel to the side wall of said groove (12) and deeper than said first conductive layer (32, 32').
Claim 11
Dependent Claim
36 words
The device according to claim 9, characterized by further comprising a semiconductive layer (46) formed in said substrate (10) to surround said groove (12), and having a conductivity type opposite to that of said substrate (10).
Claim 12
Dependent Claim
32 words
The device according to claim 10, characterized in that said semiconductive layer (46) comprises a semiconductive layer section (48) wh.ich is locally thick at the bottom portion (44) of said groove (12).
Claim 13
Dependent Claim
28 words
The device according to claim 11, characterized in that said first and second conductive layers (32, 32') are constituted by polycrystalline silicon films insulatively stacked with each other.
Claim 14
Dependent Claim
67 words
The device according to claim 12, further comprising an insulative layer (38, 102) formed to fill said groove (12) and electrically separate said first and second conductive layers (32, 32'; 36) from each other, said insulative layer (102) being deposited on the bottom portion (44) of said groove (12) to be thicker than an insulative layer portion (104) deposited on said side walls of said groove (12).
References Cited (Backward Citations)
No citation records indexed.
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