Patent US3448678A successfully refreshed from Google Patents.
Patent EP0183032A2 successfully refreshed from Google Patents.
EP0183032A2
Expired / Lapsed
EP
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High density CMOS integrated circuit manufacturing process
Assignee: Texas Instruments Inc
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Filing: 1985-10-15
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Granted: —
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Expires: 2005-10-15
Abstract
Abstract A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is provided, and a minimum of encroachment occurs. Both P-channel and N-channel transistors are constructed with silicided, ion-implanted, source/ drain regions, self-aligned to the gates, employing an implant after sidewall oxide is in place, providing lightly-doped drains. The threshold voltages of the P-channel and N-channel transistors are established by the tank implants rather than by separate ion-implant steps for threshold adjust.
Inventors
- 👤 Robert R. Doering
- 👤 Michael P. Duane
- 👤 Gregory J. Armstrong
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 08:47
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; Y; Y10; Y10S; Y10S148/00; Y10S148/082; Y10S148/14
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
244 words
A method of making a CMOS twin-well semiconductor device, comprising the steps of: implanting N impurity into a selected area of a face of a P type silicon body creating an N well area and growing a first oxide over said N well area, implanting P impurity into said face using said first oxide as a mask to create a P well area, and subjecting said body to heat treatment to drive both said N well and : P well into said face, forming an oxidation mask over said face and opening a hole in said mask within said P well area, then etching a recess into the silicon of said face in said hole, oxidizing said silicon in said recess to create a fiela oxide isolation area extending into said face, the field oxide having a top surface about level with said face, applying a layer of conductive material on said face and patterning said layer to leave gate layers on said N well and P well areas, implanting N+ impurity into both the N well and P well areas to create N+ source/drain for an N channel transistor in the P well area, using said gate layers as a mask, implanting P+ impurity into only the N well area, using the gate layer and a photoresist coating as a mask, to create P+ source/drain regions in the N well area, at a concentration much higher than that in said N+ source/drain regions.
Claim 2
Independent Claim
244 words
A method of making a CMOS twin-well semiconductor device, comprising the steps of: implanting N impurity into a selected area of a face of a P type silicon body creating an N well area and growing a first oxide over said N well area, implanting P impurity into said face using said first oxide as a mask to create a P well area, and subjecting said body to heat treatment to drive both said N well and : P well into said face, forming an oxidation mask over said face and opening a hole in said mask within said P well area, then etching a recess into the silicon of said face in said hole, oxidizing said silicon in said recess to create a fiela oxide isolation area extending into said face, the field oxide having a top surface about level with said face, applying a layer of conductive material on said face and patterning said layer to leave gate layers on said N well and P well areas, implanting N+ impurity into both the N well and P well areas to create N+ source/drain for an N channel transistor in the P well area, using said gate layers as a mask, implanting P+ impurity into only the N well area, using the gate layer and a photoresist coating as a mask, to create P+ source/drain regions in the N well area, at a concentration much higher than that in said N+ source/drain regions.
Claim 3
Dependent Claim
23 words
A method according to claim 1 including the step of forming sidewall spacers on said gate layers prior to said steps of implanting.
Claim 4
Dependent Claim
27 words
A method according to claim 1 including the step of forming a channel stop region in the bottom of said recess prior to forming said field oxide.
Claim 5
Dependent Claim
17 words
A method according to claim 1 including the step of forming direct-reacted silicide on said source/drain regions.
Claim 6
Dependent Claim
22 words
A method according to claim 4 wherein said step of forming direct-reacted silicide is masked by sidewall oxide on said gate layers.
Claim 7
Dependent Claim
27 words
A method according to claim 5 wherein said gate layers are polycrystalline silicon, and including the step of forming direct-reacted silicide on top of said gate layers.
Claim 8
Dependent Claim
28 words
A method according to claim 1 wherein said step of oxidizing said silicon in said recess includes forming an oxidation mask selectively on the sidewalls of said recess.
Claim 9
Independent Claim
263 words
A method of making a semiconductor device, comprising the steps of: implanting impurity of one type into a selected area of a face of a semiconductor body of the opposite type creating a first well area and growing a first oxide over said first well area, implanting impurity of the opposite type into said face using said first oxide as a mask to create a second well area, and subjecting said body to heat treatment to drive both said first well and second well into said face and to establish threshold voltages for transistors subsequently formed in said first and second areas, forming an oxidation mask over said face and opening a hole in said mask within said second well area, then etching a recess into said face in said hole, oxidizing said semiconductor material of said face in said recess to create a field oxide isolation area extending into said face, the field oxide having a top surface about level with said face, applying a layer of conductive material on said face an patterning said layer to leave gate layers on said first well and second well areas, implanting impurity of said one type into both the first well and second well areas to create source/drain regions for a transistor in the second well area, using said gate layers as a mask, implanting impurity of said opposite type into only the first well area, to create source/drain regions for a transistor in the first well area, at a concentration much higher than that of said source/drain regions in the second well area.
Claim 10
Independent Claim
263 words
A method of making a semiconductor device, comprising the steps of: implanting impurity of one type into a selected area of a face of a semiconductor body of the opposite type creating a first well area and growing a first oxide over said first well area, implanting impurity of the opposite type into said face using said first oxide as a mask to create a second well area, and subjecting said body to heat treatment to drive both said first well and second well into said face and to establish threshold voltages for transistors subsequently formed in said first and second areas, forming an oxidation mask over said face and opening a hole in said mask within said second well area, then etching a recess into said face in said hole, oxidizing said semiconductor material of said face in said recess to create a field oxide isolation area extending into said face, the field oxide having a top surface about level with said face, applying a layer of conductive material on said face an patterning said layer to leave gate layers on said first well and second well areas, implanting impurity of said one type into both the first well and second well areas to create source/drain regions for a transistor in the second well area, using said gate layers as a mask, implanting impurity of said opposite type into only the first well area, to create source/drain regions for a transistor in the first well area, at a concentration much higher than that of said source/drain regions in the second well area.
Claim 11
Dependent Claim
23 words
A method according to claim 8 including the step of forming sidewall spacers on said gate layers prior to said steps of implanting.
Claim 12
Dependent Claim
27 words
A method according to claim 8 including the step of forming a channel stop region in the bottom of said recess prior to forming said field oxide.
Claim 13
Dependent Claim
17 words
A method according to claim 8 including the step of forming direct-reacted silicide on said source/drain regions.
Claim 14
Dependent Claim
22 words
A method according to claim 11 wherein said step of forming direct-reacted silicide is masked by sidewall oxide on said gate layers.
Claim 15
Dependent Claim
29 words
13 . A method according to claim 12 wherein said gate layers are polycrystalline silicon, and including the step of forming direct-reacted silicide on top of said gate layers.
Claim 16
Dependent Claim
29 words
A method according to claim 8 wherein said step of oxidizing said semiconductor material in said recess Includes forming an oxidation mask selectively on the sidewalls of said recess.
Claim 17
Dependent Claim
137 words
A CMOS twin-well integrated circuit device formed in a face of a silicon body, comprising: an N well area of said face, and a P-channel transistor within said N well area, a gate for said P-channel transistor positioned over said N well area and having sidewall spacers, source and drain regions for the P-channel transistor self-aligned with said sidewall spacers on the gate, a P well area of said face, and an N-channel transistor within said N well area, a gate for said N-channel transistor positioned over said P well area and having sidewall spacers, source and drain regions for the N-channel transistor self-aligned with said sidewall spacers on the gate, a recessed oxide isolation area in said face in said P well area, the oxide isolation area having an upper surface about level with said face.
Claim 18
Dependent Claim
137 words
A CMOS twin-well integrated circuit device formed in a face of a silicon body, comprising: an N well area of said face, and a P-channel transistor within said N well area, a gate for said P-channel transistor positioned over said N well area and having sidewall spacers, source and drain regions for the P-channel transistor self-aligned with said sidewall spacers on the gate, a P well area of said face, and an N-channel transistor within said N well area, a gate for said N-channel transistor positioned over said P well area and having sidewall spacers, source and drain regions for the N-channel transistor self-aligned with said sidewall spacers on the gate, a recessed oxide isolation area in said face in said P well area, the oxide isolation area having an upper surface about level with said face.
Claim 19
Dependent Claim
36 words
16 . A device according to claim 15 wherein said P-channel and N-channel transistors have threshold voltages established by the doping of said N well and P well areas, respectively and not by threshold-adjust impurity implants.
Claim 20
Dependent Claim
17 words
A device according to claim 15 wherein said source and drain regions are clad with direct-reacted silicide.
Claim 21
Dependent Claim
16 words
A device according to claim 17 wherein said gates are polycrystalline silicon clad with direct-reacted silicide.
Claim 22
Dependent Claim
54 words
A device according to claim 16 wherein a supply voltage of +5v dc and zero are applied to terminals of said integrated circuit device and the silicon body is biased to a substrate bias of -3v dc, and wherein said threshold voltages are 1.2v for the P-channel transistor and +0.8v for the N-channel transistor.
Claim 23
Dependent Claim
78 words
A method according to claim 13 wherein said body is silicon, said impurity of one type is P type, said impurity of opposite type is N type, said transistor in the first well area is P-channel and has a threshold voltage of 1.2v, said transistor in the second well area is N-channel and has a threshold voltage of 0.8v, when a supply voltage of +5v is used for the device and a substrate bias of -3v is imposed.
References Cited (Backward Citations)
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