Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
184 words
A semiconductor device having a gate electrode (3) formed on a semiconductor substrate (11), and source (S) and drain (D) regions formed in the semiconductor substrate, characterised in that the source and drain regions each comprise a first impurity region (15a) doped with impurity of opposite conductivity type to that of the semiconductor substrate and formed at a portion adjacent an edge - (A) of the gate electrode; a second impurity region (15b) doped with impurity of opposite conductivity type to the semiconductor substrate and formed at a portion under the first impurity region, the impurity of the second impurity region having a diffusion coefficient larger than that of the impurity of the first impurity region; and a third impurity region (14) doped with impurity of opposite conductivity type to the semiconductor substrate and formed at a portion spaced from the edge of the gate electrode, the third impurity region having a higher concentration than that of the first and second impurity regions and the impurity of the third impurity region having a diffusion coefficient smaller - than that of the second impurity region.
Claim 2
Dependent Claim
184 words
A semiconductor device having a gate electrode (3) formed on a semiconductor substrate (11), and source (S) and drain (D) regions formed in the semiconductor substrate, characterised in that the source and drain regions each comprise a first impurity region (15a) doped with impurity of opposite conductivity type to that of the semiconductor substrate and formed at a portion adjacent an edge - (A) of the gate electrode; a second impurity region (15b) doped with impurity of opposite conductivity type to the semiconductor substrate and formed at a portion under the first impurity region, the impurity of the second impurity region having a diffusion coefficient larger than that of the impurity of the first impurity region; and a third impurity region (14) doped with impurity of opposite conductivity type to the semiconductor substrate and formed at a portion spaced from the edge of the gate electrode, the third impurity region having a higher concentration than that of the first and second impurity regions and the impurity of the third impurity region having a diffusion coefficient smaller - than that of the second impurity region.
Claim 3
Dependent Claim
19 words
A device according to claim 1, characterised in that the impurity in the first impurity region (15a) is arsenic.
Claim 4
Dependent Claim
47 words
3 . A device according to claim 2, characterised in that the arsenic ions are doped into the semiconductor substrate - (11) to a dosage of 1 x 10 13 to 1 x 10 15 cm -2 and at an accelerating energy of 60 to 120 KeV.
Claim 5
Independent Claim
20 words
A device according to any preceding claim, characterised in that the impurity in the second impurity region (15b) is phosphorus.
Claim 6
Dependent Claim
44 words
A device according to claim 4, characterised in that the phosphorus ions are doped into the semiconductor substrate (11) to a dosage of 1 x 10 13 to 1 x 10 15 cm -2 and at an accelerating energy of 60 to 80 KeV.
Claim 7
Independent Claim
20 words
A device according to any preceding claim, characterised in that the impurity in the third impurity region (14) is arsenic.
Claim 8
Dependent Claim
44 words
A device according to claim 6, characterised in that the arsenic ions are doped into the semiconductor substrate - (11) to a dosage of 3 x 10 15 to 5 x 10" cm- 2 and at an accelerating energy of 60 to 120 KeV.
Claim 9
Independent Claim
34 words
A device according to any preceding claim, characterised in that the spacing from the edge of the gate electrode (3) is determined by the width of a side wall (10) alongside the gate electrode.
Claim 10
Independent Claim
59 words
A device according to any preceding claim, characterised in that a junction surface formed between the first impurity region (15a) and the semiconductor substrate (11) is substantially tangential to a junction surface formed between the second impurity region (15b) and the semiconductor substrate at edges of the source and drain regions adjacent the edges of the gate electrode (3).