Protective device for integrated circuit

Claim 2

A protective device for an integrated circuit fabricated on a semiconductor substrate of a first conductivity type, comprising: a first impurity region of a second conductivity type formed in a surface portion of said semiconductor substrate and electrically connected to a terminal plate which supplies said integrated circuit with normal external voltages; and a second impurity region of the second conductivity type formed in the surface portion of said semiconductor substrate and electrically connected to a voltage supply layer to which a difference voltage i.s applied, said second impurity region being electrically insulated from said first impurity region under the normal external voltages, a current path being established between said first and second impurity regions under an application of an abnormal external voltage applied through said terminal plate.

Claim 3

A protective device as set forth in claim 1, in which said first and second impurity regions are arranged to be substantially in parallel to and at spacing from each other.

Claim 4

A protective device as set forth in claim 2, in which said first and second impurity regions are spaced apart at an interval less than or equal to about 4 microns.

Claim 5

A protective device as set forth in claim 2, in which said protective device further comprises a first intermediate conductive layer having contact areas respectively connected to said terminal plate and said first impurity region and a second intermediate conductive layer having contact areas respectively connected to said second impurity region and said voltage supply layer.

Claim 6

A protective device as set forth in claim 4, in which the surface portion of said semiconductor substrate is covered with an insulating layer, said first intermediate conductive layer passing through said insulating layer and interconnecting said first impurity region and said terminal plate which extends on the insulating layer, said second intermediate conductive layer passing through another portion of the insulating layer and interconnecting said second impurity region and said voltage supply layer which is formed on the insulating layer.

Claim 7

A protective device as set forth in claim 5, in which said terminal plate and the contact areas of said first intermediate conductive layer have respective edge portions which are substantially in parallel to said first impurity region.

Claim 8

A protective device as set forth in claim 6, in which said voltage supply layer and the contact areas of said second intermediate conductive layer have respective edge portions which are substantially in parallel to said second impurity region.

Claim 9

A protective device as set forth in claim 4, in which said first intermediate conductive layer has a length greater than or equal to about 10 microns measured between said contact areas thereof.

Claim 10

A protective device as set forth in claim 8, in which said first intermediate conductive layer causes said terminal plate to be upwardly and sidewardly spaced apart from said first impurity region.

Claim 11

A protective device as set forth in claim 9, in which said terminal plate and said first intermediate conductive layer are respectively made of aluminium and heavily doped poly silicon.

Claim 12

A protective device for an integrated circuit fabricated on a semiconductor substrate of a first conductivity type, comprising: a first impurity region of a second conductivity type formed on a surface portion of said semiconductor substrate; a second impurity region of the second conductivity type formed on the surface portion and spaced apart from said first impurity region; an insulating layer covering the surface portion and formed with first and second contact holes; first intermediate conductive layer passing through said first contact hole and interconnecting said first impurity region and a terminal plate supplying said integrated circuit with nornal external voltages; and second intermediate conductive layer passing through said second contact hole and interconnecting said second impurity region and a voltage supply layer to which a difference voltage is applied, wherein said first impurity region is electrically insulated from said second impurity region under the normal external voltages, a current path being established between said first and second regions under an application of an abnormal external voltage applied through said terminal plate.

Claim 13

A protective device for an integrated circuit fabricated on a semiconductor substrate of a first conductivity type, comprising: a first impurity region of a second conductivity type formed on a surface portion of said semiconductor substrate; a second impurity region of the second conductivity type formed on the surface portion and spaced apart from said first impurity region; an insulating layer covering the surface portion and formed with first and second contact holes; first intermediate conductive layer passing through said first contact hole and interconnecting said first impurity region and a terminal plate supplying said integrated circuit with nornal external voltages; and second intermediate conductive layer passing through said second contact hole and interconnecting said second impurity region and a voltage supply layer to which a difference voltage is applied, wherein said first impurity region is electrically insulated from said second impurity region under the normal external voltages, a current path being established between said first and second regions under an application of an abnormal external voltage applied through said terminal plate.