Patent EP0201706A2 successfully refreshed from Google Patents.
EP0201706A2
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EP
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Dynamic random access memory device having a plurality of improved one-transistor type memory cells
Assignee: NEC Corp
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Filing: 1986-04-01
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Granted: —
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Expires: 2006-04-01
Abstract
Abstract A dynamic memory device forming a plurality of one-transistor type memory cells in a semiconductor substrate is disclosed. The substrate includes a first portion of one conductivity type, and a second portion of one conductivity type having a higher impurity concentration than that of the first portion and separated from a major surface of the substrate by interposing a part of the first portion. A groove is provided from the major surface into the second portion through the part of the first portion such that a first side wall of the groove is made of the first portion and a second side wall under the first side wall and the bottom of the groove are made of the second portion. A dielectric film of the capacitor is formed on the second side wall and the bottom of the groove, and an electrode of the capacitor is formed on the dielectric film with the groove. One of source and drain regions of the opposite conductivity type of the transfer gate transistor is formed in the first portion, separated from the second portion and contact at its end section to a part of the first side wall of the groove. The electrode of the capacitor is connected to the end section of the source or drain region of the transfer gate transistor.
Inventors
- 👤 Yasuaki Hokari
- 👤 Toshiyuki Shimizu
- 👤 Mitsuru Sakamoto
- 👤 Hiroaki Mikoshiba
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 12:36
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
241 words
A dynamic memory device comprising a semiconductor substrate having a major surface, said substrate including a first portion of one conductivity type and a second portion of one conductivity type having a higher impurity concentration than that of said first portion and separated from said major surface of said substrate by interposing a part of said first portion, a groove provided from said major surface of said substrate into said second portion through said part of said first portion such that a first side wall of said groove is made of said first portion and a second side wall under said first side wall and the bottom of said groove are made of said second portion, a first insulating film formed on said second side wall of said groove and on said bottom- of said groove, an impurity region of the opposite conductivity type formed in said first portion, separated from said second portion and contacted at its end section to a part of said first side well of said groove, and a conductive member formed on said first insulating film within said groove and connected to said end section of said impurity region, whereby said first insulating film and said conductive member within said groove constitute a dielectric film and an electrode of a capacitor of a memory cell, respectively, and said impurity region is one of source and drain regions of a transfer gate transistor of said memory cell.
Claim 2
Dependent Claim
241 words
A dynamic memory device comprising a semiconductor substrate having a major surface, said substrate including a first portion of one conductivity type and a second portion of one conductivity type having a higher impurity concentration than that of said first portion and separated from said major surface of said substrate by interposing a part of said first portion, a groove provided from said major surface of said substrate into said second portion through said part of said first portion such that a first side wall of said groove is made of said first portion and a second side wall under said first side wall and the bottom of said groove are made of said second portion, a first insulating film formed on said second side wall of said groove and on said bottom- of said groove, an impurity region of the opposite conductivity type formed in said first portion, separated from said second portion and contacted at its end section to a part of said first side well of said groove, and a conductive member formed on said first insulating film within said groove and connected to said end section of said impurity region, whereby said first insulating film and said conductive member within said groove constitute a dielectric film and an electrode of a capacitor of a memory cell, respectively, and said impurity region is one of source and drain regions of a transfer gate transistor of said memory cell.
Claim 3
Dependent Claim
23 words
A dynamic memory device of Claim 1, in which said impurity concentration of said second portion is 10 18 atoms/cm 3 or more.
Claim 4
Dependent Claim
29 words
A dynamic memory device of Claim 1, in which the depth of said part of said first portion above said second portion ranges from 0.8 µm to 1.5 µm.
Claim 5
Dependent Claim
23 words
A dynamic memory device of Claim 1, in which the impurity concentration of said first portion is 10 17 atoms/cm 3 or less.
Claim 6
Dependent Claim
22 words
A dynamic memory device of Claim 1 further comprising a second insulating film formed on said first side wall of said groove.
Claim 7
Dependent Claim
169 words
A dynamic memory device comprising a semiconductor substrate, said substrate including a semiconductor body of one conductivity type having a higher impurity concentration and a semiconductor layer of one conductivity type having a lower impurity concentration and formed on said semiconductor body, a groove form in said substrate such that it extends from the upper surface of said semiconductor layer into said semiconductor body, a dielectric film formed on the side wall and on the bottom of groove, an impurity region of the opposite conductivity type formed in said semiconductor layer, separated from said semiconductor body and contact at its end section to an upper part of said groove, and an electrode formed on said dielectric film within said groove and connected to said end section of said impurity region, whereby said electrode, said dielectric film and said semiconductor body constitute a MOS type capacitor of a memory cell, and said impurity region is one of source and drain regions of a transfer gate transistor of said memory cell.
Claim 8
Dependent Claim
169 words
A dynamic memory device comprising a semiconductor substrate, said substrate including a semiconductor body of one conductivity type having a higher impurity concentration and a semiconductor layer of one conductivity type having a lower impurity concentration and formed on said semiconductor body, a groove form in said substrate such that it extends from the upper surface of said semiconductor layer into said semiconductor body, a dielectric film formed on the side wall and on the bottom of groove, an impurity region of the opposite conductivity type formed in said semiconductor layer, separated from said semiconductor body and contact at its end section to an upper part of said groove, and an electrode formed on said dielectric film within said groove and connected to said end section of said impurity region, whereby said electrode, said dielectric film and said semiconductor body constitute a MOS type capacitor of a memory cell, and said impurity region is one of source and drain regions of a transfer gate transistor of said memory cell.
Claim 9
Dependent Claim
42 words
A dynamic memory device of Claim 6, in which the impurity concentration of said semiconductor body ranges from 10 18 to 10 2 ' atoms/cm' and the impurity concentration of said semiconductor layer ranges from 10 14 to 10" atoms/cm 3 .
References Cited (Backward Citations)
No citation records indexed.
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