Semiconductor memory

Abstract

Abstract In this invention, in a sensing circuit of a dynamic memory, barrier transistors are provided between the bit lines and the sensing amplifier. A circuit is provided that, on sensing and on data transfer, changes the gate potential of the barrier transistors so that during the sensing operation the barrier transistors (1, 2) are temporarily turned OFF, so that sensing can be carried out with high sensitivity, as the sensing system is not affected by the parasitic capacitance of the bit lines, while, on data transfer to the input/output lines (I/O ,I/O ), the gate potential (φ T ) of the barrier transistors (1, 2) is raised to a level greater than a value reached by adding the threshold value (V TH ) of the MOS transistors to the power source voltage, so that the conductance of the barrier transistors (1, 2) is increased, thereby speeding up the presensing of the input/ output lines in the sensing circuit. In one embodiment a first MOS transistor (21) connects a power source (25) with a first node (φ T ) constituting the gate input of the MOS transistors (1, 2). A second MOS transistor (22) connects a node (φ SA ) which is common to a pair of MOS transistors constituting a flip-flop of the sensing circuit and a second node (N2) connected through a capacitance (24) with the first node (φ T ). A third MOS transistor (23) connects the second node (N2) in the power source (25). With this arrangement the second node (N2) discharges through the second MOS transistor (22) on the sensing operation and, on data transfer operation, recharges through the third MOS transistor (23).

Inventors

• 👤 Hiroshi C/O Patent Div. Toshiba Corp. Sahara
• 👤 Haruki C/O Patent Div. Toshiba Corp. Toda
• 👤 Shigeo C/O Patent Div. Ohshima

Bibliographic Details