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EP0206580A2
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Method and apparatus for interconnecting processors in a hyper-dimensional array
Assignee: Thinking Machines Corp
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Filing: 1986-06-04
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Granted: —
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Expires: 2006-06-04
Abstract
Abstract A massively parallel processor is described comprising 65,534 (= 2 16 ) individual processors organized so that there are 16 (= 2 4 ) individual processors on each of 4,096 (= 2 12 ) integrates circuits (120). The integrated circuits are interconnected in the form of a Boolean cube of 12 dimensions for routing of message packets. Each circuit board carries 32 (= 2 5 ) integrated circuits and each backplane (140) carries 16 (= 2 4 ) circuit boards (100). There are eight (= 2 3 ) backplanes (140) advantageously arranged in a cube that is 2x2x2. Each integrated circuit (120) on a circuit board (100) is connected to five integrated circuits (120) on the same board (100) which are its nearest neighbors in the first five dimensions. Further, each integrated circuit (120) is also connected to four other integrated circuits (120) on different circuit boards (100), but on the same backplane (140). Finally, each integrated circuit (120) is also connected to three other integrated circuits (120), each on a different backplane (140). As a result of this arrangement, all message packets are first routed to nearest neighbor ICs located on the same circuit board; all message packets are then routed to nearest neighbor ICs located on the same backplane (140); and finally, all message packets are then routed to nearest neighbor ICs located on different backplanes (140).
Inventors
- 👤 Tamiko Thiel
- 👤 Carl Feynman
- 👤 Richard Clayton
- 👤 W. Daniel Hillis
- 👤 Brewster Kahle
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 18:58
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/409; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/17343; G06F15/76; G06F15/80
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
106 words
In a parallel processor having an array of integrated circuits each of which contains at least one processor and is interconnected to each of its nearest neighbors in a space of more than three dimensions, a method of making such interconnections on a plurality of circuit boards and backplanes characterised by the steps of: interconnecting on each circuit board the integrated circuits which are nearest neighbors in dimensions one through L; interconnecting on each backplane the integrated circuits which are nearest neighbors in dimensions L+l through M; and interconnecting from one backplane to another the integrated circuits which are nearest neighbors in dimensions M+l through N.
Claim 2
Dependent Claim
106 words
In a parallel processor having an array of integrated circuits each of which contains at least one processor and is interconnected to each of its nearest neighbors in a space of more than three dimensions, a method of making such interconnections on a plurality of circuit boards and backplanes characterised by the steps of: interconnecting on each circuit board the integrated circuits which are nearest neighbors in dimensions one through L; interconnecting on each backplane the integrated circuits which are nearest neighbors in dimensions L+l through M; and interconnecting from one backplane to another the integrated circuits which are nearest neighbors in dimensions M+l through N.
Claim 3
Dependent Claim
14 words
The method of claim 1 wherein each integrated circuit contains a plurality of processors.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein the integrated circuits are connected in the form of a Boolean cube of N dimensions.
Claim 5
Dependent Claim
112 words
In a parallel processor having an array of integrated circuits each of which contains at least one processor and is interconnected to each of its nearest neighbors in a space of more than three dimensions, a method of making such interconnections on a plurality of circuit boards and backplanes characterised by the steps of: interconnecting on each circuit board the integrated circuits which are nearest neighbors in a first consecutive number of dimensions; interconnecting on each backplane the integrated circuits which are nearest neighbors in a second consecutive number of dimensions; and interconnecting from one backplane to another the integrated circuits which are nearest neighbors in a third consecutive number of dimensions.
Claim 6
Dependent Claim
112 words
In a parallel processor having an array of integrated circuits each of which contains at least one processor and is interconnected to each of its nearest neighbors in a space of more than three dimensions, a method of making such interconnections on a plurality of circuit boards and backplanes characterised by the steps of: interconnecting on each circuit board the integrated circuits which are nearest neighbors in a first consecutive number of dimensions; interconnecting on each backplane the integrated circuits which are nearest neighbors in a second consecutive number of dimensions; and interconnecting from one backplane to another the integrated circuits which are nearest neighbors in a third consecutive number of dimensions.
Claim 7
Dependent Claim
14 words
The method of claim 4 wherein each integrated circuit contains a plurality of processors.
Claim 8
Dependent Claim
21 words
The method of claim 4 wherein the integrated circuits are connected in the form of a Boolean cube of N dimensions.
Claim 9
Dependent Claim
118 words
In a parallel processor having an array of integrated circuits (120) each of which contains at least one processor and is interconnected to each of its nearest neighbors in a space of more than three dimensions, apparatus for interconnecting said integrated circuits (120) on a plurality of boards (100) and backplanes (140) comprising: means for interconnecting (130) on each circuit board (100) the integrated circuits (120) which are nearest neighbors in dimensions one through L; means for interconnecting (130) on each backplane(140)the integrated lcircuits (120) which are nearest neighbors in dimensions L+l through M; and means for interconnecting (150) from one backplane (140) to another the integrated circuits (120) which are nearest neighbors in dimensions M+l through N.
Claim 10
Dependent Claim
118 words
In a parallel processor having an array of integrated circuits (120) each of which contains at least one processor and is interconnected to each of its nearest neighbors in a space of more than three dimensions, apparatus for interconnecting said integrated circuits (120) on a plurality of boards (100) and backplanes (140) comprising: means for interconnecting (130) on each circuit board (100) the integrated circuits (120) which are nearest neighbors in dimensions one through L; means for interconnecting (130) on each backplane(140)the integrated lcircuits (120) which are nearest neighbors in dimensions L+l through M; and means for interconnecting (150) from one backplane (140) to another the integrated circuits (120) which are nearest neighbors in dimensions M+l through N.
Claim 11
Dependent Claim
15 words
The apparatus of claim 7 wherein each integrated circuit (120) contains a plurality of processors.
Claim 12
Dependent Claim
22 words
The apparatus of claim 7 wherein the integrated circuits (120) are connected in the form of a Boolean cube of N dimensions.
Claim 13
Dependent Claim
45 words
The apparatus of claim 7 wherein the means for interconnecting (150) integrated circuits on a backplane (140) comprises means for interconnecting integrated circuits (120) on each board (100) connected to a backplane (140) to integrated circuits on other boards connected to the same backplane (140).
Claim 14
Dependent Claim
81 words
The apparatus of claim 7 wherein at least eight integrated circuits (120) are mounted on a circuit board (100) with each integrated circuit (120) being connected to at least three nearest neighbors on that board, said eight integrated circuits being arranged in an array of two columns and four rows with each integrated circuit in a top half of the array being connected to two other integrated circuits in the top half and one other integrated circuit in the bottom half.
Claim 15
Dependent Claim
122 words
In a parallel processor having an array of integrated circuits (120) each of which contains at least one processor and is interconnected to each of its nearest neighbors in a space of more than three dimensions, apparatus (150) for interconnecting said integrated circuits on a plurality of boards and backplanes comprising: means for interconnecting (130) on each circuit board (110) the integrated circuits (120) which are nearest neighbors in a first consecutive number of dimensions; means for interconnecting (130) on each backplane (140) the integrated circuits which are nearest neighbors in a second consecutive number of dimensions; and means for interconnecting (150) from one backplane to another the integrated circuits (120) which are nearest neighbors in a third consecutive number of dimensions.
Claim 16
Dependent Claim
122 words
In a parallel processor having an array of integrated circuits (120) each of which contains at least one processor and is interconnected to each of its nearest neighbors in a space of more than three dimensions, apparatus (150) for interconnecting said integrated circuits on a plurality of boards and backplanes comprising: means for interconnecting (130) on each circuit board (110) the integrated circuits (120) which are nearest neighbors in a first consecutive number of dimensions; means for interconnecting (130) on each backplane (140) the integrated circuits which are nearest neighbors in a second consecutive number of dimensions; and means for interconnecting (150) from one backplane to another the integrated circuits (120) which are nearest neighbors in a third consecutive number of dimensions.
Claim 17
Dependent Claim
15 words
The apparatus of claim 12 wherein each integrated circuit (120) contains a plurality of processors.
Claim 18
Dependent Claim
21 words
The apparatus of claim 12 wherein the integrated circuits are connected in the form of a Boolean cube of N dimensions.
Claim 19
Dependent Claim
44 words
The apparatus of claim 12 wherein the means for interconnecting (150) integrated circuits on a backplane comprises means for interconnecting integrated circuits on each board (100) connected to a backplane (140) to integrated circuits (120) on other boards connected to the same backplane (140).
Claim 20
Dependent Claim
80 words
The apparatus of claim 12 wherein at least eight integrated circuits are mounted on a circuit board (100) with each integrated circuit (120) being connected to at least three nearest neighbors on that board, said eight integrated circuits being arranged in an array of two columns and four rows with each integrated circuit in a top half of the array being connected to two other integrated circuits in the top half and one other integrated circuit in the bottom half.
References Cited (Backward Citations)
No citation records indexed.
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