Memory system and interface therein

Claim 2

An input/output interface in a memory system to read or write data through data lines, said memory interface comprising: a first data buffer serving as a data input/output interface in a word direction; a.second data buffer serving as an input/ output interface in a bit direction and also adapted to operate independent of said word-direction data buffer; data buffer select means for selecting either of said two data buffers; and, direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system.

Claim 3

A memory system to read or write data through data lines, comprising a word-direction data buffer serving as a data input/output interface in a word direction; - a bit-direction data buffer serving as an input/ output interface in a bit direction and also adapted to operate independent of said word-direction data buffer; data buffer select means for selecting either of said two data buffers; and, direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system.

Claim 4

A memory system to read or write data through data lines, comprising a word-direction data buffer serving as a data input/output interface in a word direction; - a bit-direction data buffer serving as an input/ output interface in a bit direction and also adapted to operate independent of said word-direction data buffer; data buffer select means for selecting either of said two data buffers; and, direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system.

Claim 5

A memory system to read or write data through data lines, characterized in that there are provided a plurality of memory interfaces, each comprising a word-direction data buffer serving as a word-direction input/output interface, a bit-direction input/output interface and also adapted to operate independent of said word-direction data buffer, data buffer select means for selecting either of said two data buffers, and direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system, and also that a plurality of memories are arranged two-dimensionally through said plurality of memory interfaces, respectively.

Claim 6

A memory system to read or write data through data lines, characterized in that there are provided a plurality of memory interfaces, each comprising a word-direction data buffer serving as a word-direction input/output interface, a bit-direction input/output interface and also adapted to operate independent of said word-direction data buffer, data buffer select means for selecting either of said two data buffers, and direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system, and also that a plurality of memories are arranged two-dimensionally through said plurality of memory interfaces, respectively.

Claim 7

A memory system to read or write data through data lines, including a memory array including a plurality of memory interfaces and a plurality of memories arranged two-dimensionally through said pluarality of memory interfaces, each of said memory interfaces comprising a word-direction data buffer serving as a word-direction input/output interface, a bit-direction input/output interface and also adapted to operate independent of said word-direction data buffer, data buffer select means for selecting either of said two data buffers, and direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system; word-direction inhibit mask means for inhibit masking a reading or writing operation on said memories existing in a word direction within said memory array; and, bit-direction inhibit mask means for inhibit masking a reading or writing operation on said memories existing in a bit direction within said memory array, characterized in that at least one of word-direction access-and bit-direction access is executed in accordance with select information from said data buffer select means and setting of data by said mask means.

Claim 8

A memory system to read or write data through data lines, including a memory array including a plurality of memory interfaces and a plurality of memories arranged two-dimensionally through said pluarality of memory interfaces, each of said memory interfaces comprising a word-direction data buffer serving as a word-direction input/output interface, a bit-direction input/output interface and also adapted to operate independent of said word-direction data buffer, data buffer select means for selecting either of said two data buffers, and direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system; word-direction inhibit mask means for inhibit masking a reading or writing operation on said memories existing in a word direction within said memory array; and, bit-direction inhibit mask means for inhibit masking a reading or writing operation on said memories existing in a bit direction within said memory array, characterized in that at least one of word-direction access-and bit-direction access is executed in accordance with select information from said data buffer select means and setting of data by said mask means.

Claim 9

A memory system as set forth in Claim 4, in which said memory array includes a plurality of input/output signal lines extending in a word direction in said memory array and a plurality of input/output signal lines extending in a bit direction in said memory array, said word-direction input/output signal lines being connected to said bit-direction input/output signal lines, 1 to 1, in corresponding order.

Claim 10

A memory system as set forth in Claim 4, in which the number of bits in said word direction is greater than the number of bits in said bit direction.

Claim 11

A memory system as set forth in Claim 4, in which the number of bits in said word direction is smaller than the number of bits in said bit direction.

Claim 12

A memory system to read or write data through data lines, said memory system comprising: a memory array including a plurality of memory interfaces and a plurality of memories arranged one-dimen- tionally in a word direction via said memory interfaces, each of said memory interfaces comprising a word-direction data buffer serving as a word-direction input/output interface, a bit-direction data buffer serving as a bit-direction input/output interface and also adapted to operate independent of said word-direction data buffer, data buffer select means for selecting either of said two data buffers, and direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system; connecting means for dividing said memory array into a plurality of pixels and connecting said memories to one another among the corresponding bits of said pixels; and, pixel access execution means for executing pixel access in units of said pixels.

Claim 13

A memory system to read or write data through data lines, said memory system comprising: a memory array including a plurality of memory interfaces and a plurality of memories arranged one-dimen- tionally in a word direction via said memory interfaces, each of said memory interfaces comprising a word-direction data buffer serving as a word-direction input/output interface, a bit-direction data buffer serving as a bit-direction input/output interface and also adapted to operate independent of said word-direction data buffer, data buffer select means for selecting either of said two data buffers, and direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system; connecting means for dividing said memory array into a plurality of pixels and connecting said memories to one another among the corresponding bits of said pixels; and, pixel access execution means for executing pixel access in units of said pixels.

Claim 14

A memory system to read or write data through data lines, including a memory array including a plurality of memory interfaces and a plurality of memories arranged two-dimensionally via said memory interfaces, each of said memory interfaces comprising a word-direction data buffer serving as a word-direction input/output interface, a bit-direction data buffer serving as a bit-direction input/output interface and also adapted to operate independent of said word-direction data buffer, data buffer select means for selecting either of said two data buffers, and direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system; a word-direction read inhibit mask means for inhibit masking a reading operation on given ones of said memories existing in a word direction within said memory array; word-direction write inhibit mask means for inhibit masking a writing operation on given ones of said memories existing in said word direction within said memory array; and, bit-direction inhibit mask means for inhibit masking a reading or writing operation on given ones of said memories existing in a bit direction within said memory array, characterized in that at least one of word-direction access and bit-direction access is executed in accordance with select information from said data buffer select means as well as with setting of data by said mask means.

Claim 15

A memory system to read or write data through data lines, including a memory array including a plurality of memory interfaces and a plurality of memories arranged two-dimensionally via said memory interfaces, each of said memory interfaces comprising a word-direction data buffer serving as a word-direction input/output interface, a bit-direction data buffer serving as a bit-direction input/output interface and also adapted to operate independent of said word-direction data buffer, data buffer select means for selecting either of said two data buffers, and direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system; a word-direction read inhibit mask means for inhibit masking a reading operation on given ones of said memories existing in a word direction within said memory array; word-direction write inhibit mask means for inhibit masking a writing operation on given ones of said memories existing in said word direction within said memory array; and, bit-direction inhibit mask means for inhibit masking a reading or writing operation on given ones of said memories existing in a bit direction within said memory array, characterized in that at least one of word-direction access and bit-direction access is executed in accordance with select information from said data buffer select means as well as with setting of data by said mask means.

Claim 16

A memory system as set forth in Claim 9, in which said memory array includes a plurality of input/output signal lines extending in said word direction in said memory array and a plurality of input/output signal lines extending in said bit direction in said memory array, said word-direction input/output signal lines being respectively connected to said bit-direction input/output signal lines, 1 to 1, in corresponding order.

Claim 17

A memory system as set forth in Claim 9, in which the number of bits in said word direction is different from the number of bits in said bit direction.

Claim 18

An input/output interface in a memory system to read or write data through data lines, said interface comprising: signal invert means for inverting the output signals of a memory independent of one another; and, AND means for wired ANDing said memory output signals for each bit on a data bus.

Claim 19

An input/output interface in a memory system to read or write data through data lines, said interface comprising: signal invert means for inverting the output signals of a memory independent of one another; and, AND means for wired ANDing said memory output signals for each bit on a data bus.

Claim 20

A memory system to read or write data through data lines, said memory system comprising: a plurality of memory interfaces, each including signal invert means for inverting the output signals of a memory independent of one another and AND means for wired ANDing said memory output signals for each bit on a data bus; and, a plurality of said memories being arranged two-dimensionally via said memory interfaces, respectively.

Claim 21

A memory system to read or write data through data lines, said memory system comprising: a plurality of memory interfaces, each including signal invert means for inverting the output signals of a memory independent of one another and AND means for wired ANDing said memory output signals for each bit on a data bus; and, a plurality of said memories being arranged two-dimensionally via said memory interfaces, respectively.

Claim 22

An input/output interface in a memory system to read or write data through data lines, said input/output interface comprising: a memory array including a plurality of memory interfaces and a plurality of memories arranged two-dimensionally via said memory interfaces respectively, each of said memory interfaces comprising a word-direction data buffer serving as a word-direction input/output interface, a bit-direction data buffer serving as a bit-direction input/output interface and also adapted to operate independent of said word-direction data buffer, data buffer select means for selecting either of said two data buffers, and direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system; signal invert means for inverting the output signals of said memories independent of one another; and, AND means for wired ANDing said memory output signals for each bit on a data bus.

Claim 23

An input/output interface in a memory system to read or write data through data lines, said input/output interface comprising: a memory array including a plurality of memory interfaces and a plurality of memories arranged two-dimensionally via said memory interfaces respectively, each of said memory interfaces comprising a word-direction data buffer serving as a word-direction input/output interface, a bit-direction data buffer serving as a bit-direction input/output interface and also adapted to operate independent of said word-direction data buffer, data buffer select means for selecting either of said two data buffers, and direction control means for controlling the direction of each of said two data buffers in accordance with a reading or writing operation on the memory contents of said memory system; signal invert means for inverting the output signals of said memories independent of one another; and, AND means for wired ANDing said memory output signals for each bit on a data bus.

Claim 24

- An input/output interface as set forth in Claim 14, in which said memory array includes a plurality of input/output signal lines extending in said word direction in said memory array and a plurality of input/output signal lines extending in said bit direction in said memory array, said word-direction input/output signal lines being connected respectively to said bit-direction input/output signal lines, 1 to 1, in corresponding order.

Claim 25

An input/output interface as set forth in Claim 14, in which the number of bits in said word direction is different from the number of bits in said bit direction.

Claim 26

An input/output interface as set forth in Claim 14, in which said input/output interface is for said word direction and said data buffer is for said word direction.

Claim 27

An input/output interface as set forth in Claim 14, in which said signal invert means is adapted to invert the output signals of said memories for each screen.

Claim 28

An input/output interface as set forth in Claim 14, in which said inverted signals are inverted color code signals.

Claim 29

A memory system comprising: command receive cycle instruct means for allowing said memory system to receive memory commands given to said memory system; and, a command register for storing the values of address lines as said memory commands.

Claim 30

A memory system comprising: command receive cycle instruct means for allowing said memory system to receive memory commands given to said memory system; and, a command register for storing the values of address lines as said memory commands.

Claim 31

A memory system as set forth in Claim,20, in which, at the fall time of a row address strobe signal, when the levels of a column address strobe signal and a write enable signal become low, a command cycle is executed, while, at the fall time of said row address strobe signal, when said column address strobe signal and said write enable signal are in other conditions than said levels, other cycles are executed.

Claim 32

A memory system, characterized in that access as an image memory and access as a program memory can be switched over to each other according to the levels of a write enable signal at the fall time of a row address strobe signal.

Claim 33

A memory system, characterized in that access as an image memory and access as a program memory can be switched over to each other according to the levels of a write enable signal at the fall time of a row address strobe signal.

Claim 34

A memory system to execute an image memory access and a program memory access, characterized by chip select means.

Claim 35

A memory system to execute an image memory access and a program memory access, characterized by chip select means.

Claim 36

A memory system as set forth in Claim 23, in which said chip select means includes means for supplying chip select information via a data line.

Claim 37

A memory system as set forth in Claim 23, in which said chip select means includes a word-direction chip select means.

Claim 38

A memory system as set forth in Claim 23, in which said chip select means includes a plane-direction chip select means forming an image memory.

Claim 39

A memory system as set forth in Claim 23, in which said chip select means includes means for supplying chip select information via a data line and a word-direction chip select means at the same time.

Claim 40

A memory system as set forth in Claim 23, in which said chip select means includes means for supplying chip select information via a data line and a plane-direction chip select means forming an image memory at the same time.

Claim 41

A memory system as set forth in Claim 22, in which, for said program memory access, chip select information is input to a bit-direction terminals provided in said memory system, and, for said image memory access, bit mask and plane mask can be executed.