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EP0212451A2
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A semiconductor memory device having two column transfer gate transistor groups independently provided for a sense amplifier and a programming circuit
Assignee: Fujitsu Ltd
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Filing: 1986-08-06
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Granted: —
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Expires: 2006-08-06
Abstract
Abstract A semiconductor memory device, including a plurality of programmable read only memory cells arranged at intersection points of a matrix formed by a plurality of word-lines and that of bit-lines crossed each other, independently having first column transfer gate transistors locating between a programming circuit and the bit-lines to transfer a programming data signal from the programming circuit to a selected memory cell located on one of the bit-lines when the memory device is in a programming mode and second column transfer gate transistors locating between a sense amplifier and the bit-lines to transfer a read out data signal from a selected memory cell located on one of the bit-lines to a sensing amplifier when the memory device is in a reading mode.
Inventors
- 👤 Masanobu Yoshida
- 👤 Mitsuo Higuchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 16:30
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C16/00; G11C16/02; G11C16/06; G11C16/24; G11C16/26; G11C17/00; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
321 words
A semiconductor memory device to which a datum, given from the exterior of said memory device, is programmed by a programming address signal given from the exterior of said memory device when said memory device is in a programming mode in which a datum is programmed into said memory device, and from which a datum, stored in said memory device, is read out to the exterior of said memory device by a reading address signal given from the exterior of said memory device when said memory device is in a reading mode in which a datum is read out from said memory device, said memory device comprising: a plurality of word-lines; a plurality of bit-lines extending accross said word-lines to form a plurality of intersection points a plurality of memory cells formed at said intersection points; a column decoder means for providing a first column selecting signal in response to said programming address signal when said memory device is in said programming mode and a second column selecting signal in response to said reading address signal when said memory device is in said reading mode; a programming circuit for providing a selected memory cell with a data signal corresponding to said datum given from the exterior of said memory device when said memory device is in said programming mode; a sense amplifier for amplifying a data signal obtained from said datum read out from a selected memory cell when said memory device is in said reading mode; a plurality of first column transfer gate transistors for selectively connecting a selected bit-line to said programming circuit in response to said first column selecting signal during said programming mode, said first column transfer gate transistors being made non-conductive during said reading mode; and a plurality of second column transfer gate transistors for selectively connecting a selected bit-line to said sense amplifier in response to said second column selecting signal during said reading mode.
Claim 2
Dependent Claim
321 words
A semiconductor memory device to which a datum, given from the exterior of said memory device, is programmed by a programming address signal given from the exterior of said memory device when said memory device is in a programming mode in which a datum is programmed into said memory device, and from which a datum, stored in said memory device, is read out to the exterior of said memory device by a reading address signal given from the exterior of said memory device when said memory device is in a reading mode in which a datum is read out from said memory device, said memory device comprising: a plurality of word-lines; a plurality of bit-lines extending accross said word-lines to form a plurality of intersection points a plurality of memory cells formed at said intersection points; a column decoder means for providing a first column selecting signal in response to said programming address signal when said memory device is in said programming mode and a second column selecting signal in response to said reading address signal when said memory device is in said reading mode; a programming circuit for providing a selected memory cell with a data signal corresponding to said datum given from the exterior of said memory device when said memory device is in said programming mode; a sense amplifier for amplifying a data signal obtained from said datum read out from a selected memory cell when said memory device is in said reading mode; a plurality of first column transfer gate transistors for selectively connecting a selected bit-line to said programming circuit in response to said first column selecting signal during said programming mode, said first column transfer gate transistors being made non-conductive during said reading mode; and a plurality of second column transfer gate transistors for selectively connecting a selected bit-line to said sense amplifier in response to said second column selecting signal during said reading mode.
Claim 3
Dependent Claim
44 words
A semiconductor memory device according to claim 1, wherein said first column transfer gate transistor comprises a metal oxide semiconductor transistor having a drain connected to said bit-line, a source connected to said programming circuit, and a gate connected to said column decoder means.
Claim 4
Dependent Claim
46 words
A semiconductor memory device according to claim 1 or 2, wherein said second column transfer gate transistor comprises a metal oxide semiconductor transistor having a drain connected to said bit-line, a source connected to said sensing amplifier, and a gate connected to said column decoder means.
References Cited (Backward Citations)
No citation records indexed.
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