Bus state control circuit

Claim 2

A bus state control circuit comprising: a first means for receiving an access request signal supplied thereto; and second means for starting the access of an input-­output device after a predetermined time interval in the case when a previous access was made to the input-output device, and starting the access immediately in the case when the previous access was made to a device except for the input-output device or the previous access was made to the input-output device but a predetermined time has passed, at a point in time when said access request signal indicates the access of the input-output device.

Claim 3

A bus state control circuit according to claim 1, wherein said first means includes a storage means for storing said access request signal signifying the access to the input-output device for a predetermined time.

Claim 4

A bus state control circuit responsive to first clock signals, access request signals, second clock signals and input-output device access signals, comprising: first delay means which outputs a plurality of bus state signals in response to a first clock signals; second delay means coupled to said first delay means for generating a plurality of second delay signals corresponding to the output of said first delay means in response to said second clock signals; third delay means responsive to said device access signal for generating third delay signals for one clock period; and logic means connected to said first delay means and said second delay means, and being responsive to said access request signals and said input-output device access signals, for deciding next bus states and supplying signals representing such states to said first delay means in response to the outputs of said second delay means, said access request signal, and said second and third delay signals.

Claim 5

A bus state control circuit responsive to first clock signals, access request signals, second clock signals and input-output device access signals, comprising: first delay means which outputs a plurality of bus state signals in response to a first clock signals; second delay means coupled to said first delay means for generating a plurality of second delay signals corresponding to the output of said first delay means in response to said second clock signals; third delay means responsive to said device access signal for generating third delay signals for one clock period; and logic means connected to said first delay means and said second delay means, and being responsive to said access request signals and said input-output device access signals, for deciding next bus states and supplying signals representing such states to said first delay means in response to the outputs of said second delay means, said access request signal, and said second and third delay signals.

Claim 6

A bus state control circuit according to claim 3, wherein said first delay means comprises a plurality of delay circuits.

Claim 7

A bus state control circuit according to claim 3, wherein said first delay means are D-type flip-flops.

Claim 8

A bus state control circuit according to claim 3, wherein said second delay means and said first delay means are comprised of an equal number of D-type flip-flops.

Claim 9

A bus state control circuit according to claim 3, wherein said third delay means is comprised of a first D-type flip-flop operable in response to said first clock signal and a second D-type flip-flop serially connected to said first D-type flip-flop and operable in response to said second clock signal.

Claim 10

A bus state control circuit according to claim 4, wherein said logic means supplies the bus state signals TI, T1, T2, T3 and TR for states S₁ through S₁₀ according to the following truth table:

Claim 11

A bus state control circuit provided in a micro­processor to be coupled to an input-output control unit, comprising: a strobe signal generating circuit generating a strobe signal to be applied to said input-output control unit for indicating the time when an access to said input-output is possible; first means for controlling the start timing of said strobe signal; second means for controlling the end timing of said strobe signal; and third means for delaying said start timing during a predetermined period of time.

Claim 12

A bus state control circuit provided in a micro­processor to be coupled to an input-output control unit, comprising: a strobe signal generating circuit generating a strobe signal to be applied to said input-output control unit for indicating the time when an access to said input-output is possible; first means for controlling the start timing of said strobe signal; second means for controlling the end timing of said strobe signal; and third means for delaying said start timing during a predetermined period of time.

Claim 13

A bus state control circuit as claimed in claim 9, wherein said third means are enabled only when said input-­output control unit is successively accessed.