Memory cells for integrated circuits

Claim 2

A memory cell for an integrated circuit having means for biasing an array of such memory cells, comprising: a semiconductor device for storing an electrical charge representing a data bit, coupled to said biasing means to be biased into a snap-back condition such that said data bit is erased from said cell.

Claim 3

The memory cell as set forth in claim 1, wherein said semiconductor device comprises: a transistor having a floating gate for storing said data bit, such that said cell is erased by hot-hole injection onto said floating gate during said snap-back condition.

Claim 4

A semiconductor integrated circuit memory component, comprising: a metal-oxide-semiconductor field effect transistor, having a floating gate for storing an electrical charge representing a data bit, essentially nondestructively bias- able into a snap-back mode such that hot-hole injection onto said floating gate neutralizes said electrical charge, whereby said data bit is erased.

Claim 5

A semiconductor integrated circuit memory component, comprising: a metal-oxide-semiconductor field effect transistor, having a floating gate for storing an electrical charge representing a data bit, essentially nondestructively bias- able into a snap-back mode such that hot-hole injection onto said floating gate neutralizes said electrical charge, whereby said data bit is erased.

Claim 6

A single component memory cell for a semiconductor integrated circuit, having circuitry for providing a plurality of predetermined electrical signals to said cell, comprising: a substrate having a first conductivity type; a first region in said substrate having a second conductivity type, coupled to said circuitry; a second region in said substrate, having said second conductivity type, coupled to said circuitry; a third region in said substrate between said first region and said second region; an insulated, semiconductive element superposing said third region for storing electrical carriers of said second conductivity type to represent a data bit; an insulated, conductive element, superposing said semiconductive element, coupled to said circuitry, wherein said predetermined electrical signals from said circuitry cause electrical carriers of said first conductivity type to transfer from said third region to said semiconductive element, whereby said electrical carriers of said second conductivity type on said semiconductive element are neutralized.

Claim 7

A single component memory cell for a semiconductor integrated circuit, having circuitry for providing a plurality of predetermined electrical signals to said cell, comprising: a substrate having a first conductivity type; a first region in said substrate having a second conductivity type, coupled to said circuitry; a second region in said substrate, having said second conductivity type, coupled to said circuitry; a third region in said substrate between said first region and said second region; an insulated, semiconductive element superposing said third region for storing electrical carriers of said second conductivity type to represent a data bit; an insulated, conductive element, superposing said semiconductive element, coupled to said circuitry, wherein said predetermined electrical signals from said circuitry cause electrical carriers of said first conductivity type to transfer from said third region to said semiconductive element, whereby said electrical carriers of said second conductivity type on said semiconductive element are neutralized.

Claim 8

The cell as set forth in claim 4, wherein said first region comprises a MOSFET drain.

Claim 9

The cell as set forth in claim 5, wherein said second region comprises a MOSFET source.

Claim 10

The cell as set forth in claim 6, wherein said third region comprises a MOSFET channel.

Claim 11

The cell as set forth in claim 7, wherein said semiconductive element comprises a MOSFET floating gate.

Claim 12

The cell as set forth in claim 8, wherein said conductive element comprises a MOSFET control gate.

Claim 13

In an electrically erasable programmable read only memory integrated circuit device, having means for producing a plurality of reference potentials, an improved memory cell characterized by: a substrate having a first conductivity type; a drain region in said substrate having a second conductivity type; a source region in said substrate having said second conductivity type; a channel region between said source region and said drain region; a dielectric layer superposing said substrate; a first gate region in said dielectric layer superposing said channel region, for storing an electrical charge representifig a bit of data; and a second gate region in said dielectric layer superposing and separated from said first gate layer, wherein said drain region, source region, and second gate region are coupled to said producing means such that said cell is biased into a snap-back condition to erase said data bit.

Claim 14

In an electrically erasable programmable read only memory integrated circuit device, having means for producing a plurality of reference potentials, an improved memory cell characterized by: a substrate having a first conductivity type; a drain region in said substrate having a second conductivity type; a source region in said substrate having said second conductivity type; a channel region between said source region and said drain region; a dielectric layer superposing said substrate; a first gate region in said dielectric layer superposing said channel region, for storing an electrical charge representifig a bit of data; and a second gate region in said dielectric layer superposing and separated from said first gate layer, wherein said drain region, source region, and second gate region are coupled to said producing means such that said cell is biased into a snap-back condition to erase said data bit.

Claim 15

The memory cell as set forth in claim 10, wherein said first gate region accepts hot-holes from said channel region during said snap-back condition biasing first gate means to neutralize said electrical charge and erase said data bit.

Claim 16

The cell as set forth in claim 11, wherein said drain region is coupled to receive a first electrical potential bias from said producing means.

Claim 17

The cell as set forth in claim 12, wherein said source region is coupled to an electrical ground potential for said device.

Claim 18

The cell as set forth in claim 13, wherein said second gate means is coupled to receive a second electrical potential bias from said producing means, whereby said biases force said cell into a snap-back condition.

Claim 21

The method as set forth in claim 15, wherein said step of hot-hole injection further comprises: biasing said cell into a snap-back mode.

Claim 24

The method as set forth in claim 17, wherein said transistor is an n channel type, said step of biasing said source further comprises: coupling said source to the cell ground potential.

Claim 25

The method as set forth in claim 18, wherein said step of biasing said drain further comprises: coupling said source to a first positive potential for approximately 1 second.

Claim 26

The method as set forth in claim 19, wherein said step of pulsing further comprises: coupling said control gate to a second positive potential of approximately twice the magnitude of said first positive potential for approximately 1 millisecond.