Image processing system

Claim 2

Image processing system with at least a sender station (SC) and a receiver station (RC), said sender station including means (VSE, ADC) generator sets of signals (Y), each set relating at least to the image elements of an image area (AA), control means (CC) for subdividing the signals of each set into groups corresponding to blocks of said image area, means (END) for encoding said groups of signals, and means (NIC, PSNW) for transmitting the thus obtained groups of encoded signals (E1, E2) to said receiving station (RC) which include means (DEC1/2, DAC) for reconstructing said image area (AA) by making use of said encoded signals, characterized in that said control means (CC) are able to change said subdivision with respect to a previous subdivision (Figs. 4, 6).

Claim 3

Image processing system according to claim 1, characterized in that said transmission means (NIC, PSNW) transmit a signal (DX, DY Fig. 3) indicative of said subdivision to said receiving station (RC, Fig. 6) to enable said image reconstruction to be performed therein.

Claim 4

Image processing system according to claim 1., characterized in that the signals of each of said sets relate at least to a grid (GR) which incorporates said image area (AA), and that said control means (CC) also subdivide the signals of each set into groups corresponding to blocks of said grid (GR), said grid blocks also subdividing said image area (AA) into said image blocks (Figs. 2, 3).

Claim 5

Image processing system according to claim 3, characterized in that the signals of each of said sets relate at least to a scanning field (SF, Figs. 2, 3) which incorporates a said grid (GR) and that said control means (CC) provide control signals (BX, BY, PX, PY, ACT), to perform said subdivision, which relate to said grid (GR) having in said scanning field (SF) a position indicated by said indicative signal (DX, DY)(Figs. 2, 3).

Claim 6

Image processing system according to claim 4., characterized in that successive grids (GR) have different positions in the corresponding scanning fields (SF) which all have a same fixed position and that the image areas (AA) have a same fixed position in the corresponding scanning fields (SF)(Figs. 2, 3).

Claim 7

Image processing system according to claim 4, characterized in that said signal indicative of said grid position is constituted by the coordinates (DX, DY) of a vertex (GO) of said grid (GR) in a rectangular region (DR), said grid being subdivided in square blocks and said region (DR) having a vertex (DO) with fixed coordinates (DOX, DOY) in said fixedly positioned scanning fields (SF) which are also rectangular, and that a vertex (AO) of said image area (AA), which is also rectangular, has coordinates (D) in said rectangular region (DR) which are each equal to the width of a square grid block less the distance between two adjacent image elements, said vertex (GO) of said grid (GR) being displaceable between the positions of the vertexes (DO, AO) of said region (DR) and of said image area (AA)(Figs. 2, 3).

Claim 8

Image processing system according to claim 2., characterized in that said control means (CC) include first memory means (ROM) storing a series of successive indicative signals (DXl, DYl - DXn, Dyn) to be used in successive subdivision operations and communicated to said receiver station (RC), and that said receiver station (RC) includes processor means (PM) with a hit counter (HC), a miss counter (MC), second memory means (ROM1) also storing said series of successive indicative signals (DXl, DYl - DXn, DYn), and a processor circuit (PC) which at regular intervals (FPP) compares the received indicative signal (DX, DY) with an indicative signal selected during a previous interval and selects in said series the indicative signal following the received indicative signal to be used in a following interval, and that said processor circuit (PC) is able to execute a first (OUT-SYNC) or a second (IN-SYNC) algorithm, said first algorithm consisting in incrementing said hit counter (HC) and resetting said miss counter (MC) when said comparison is successful or not respectively and in starting the execution of said second algorithm when said hit counter (HC) has counted a predetermined first value, the received indicative signal being then used for controlling said image reconstruction, and said second algorithm consisting in resetting said hit counter (HC) and incrementing said miss counter (MC) when said comparison is successful or not respectively and in starting the execution of said first algorithm when said miss counter (MC) has counted a predetermined second value (Figs. 4, 6).

Claim 9

Image processing system according to claim 1, characterized in that said encoder means (END) provide at their output (E1, E2) a bitstream having a variable bitrate which is transmitted to said receiver station (RC) by said transmission means (NIC, PSNW)(Fig. 4).

Claim 10

Image processing system according to claim 8., characterized in that said encoder means (END) include the cascade connection of a differential pulse code modulator circuit (DPCM) and an entropy encoder (ECC) (Fig. 5).

Claim 11

Image processing system according to claim 9., characterized in that said transmission means (NIC, PSNW) include a packet switching network (PSNW) as well as an interface circuit (NIC) which supplies said bitstream with variable bitrate to said network under the form of packets (Fig. 4).

Claim 12

Image processing system according to claim 10., characterized in that said transmission means (NIC, PSNW) also transmit to said receiver station (RC) control signals (PX, PY), indicative of said blocks, and reference signals (flags)(Fig. 4).

Claim 13

Image processing system according to claim 3, characterized in that said encoder means (END) are controlled by said control means (CC) in such a way that said signals relating to a said image block are encoded only when the signals relating to the grid block in which this image block is incorporated satisfy a predetermined criterion, as indicated by an activated block replenishment signal (RCS)(Fig. 5)

Claim 14

Image processing system according to claim 5 or 6, and to claim 12 characterized in that said signal generating means (VSE, ADC) include a video source equipment (VSE) producing analog video signals for the image elements of each scanning field (SF) and an analog-to-digital converter (ADC) for converting said analog video signals into digital video signals (Y), that said control means (CC) include means (SCC) for deriving a clock signal (CL) from said analog video signals and counter means which are driven by said clock signal (CL) and controlled by said indicative signals (DX, DY) to provide in said grid (GR) the coordinates (BX, BY, PX, PY) of said grid blocks and image elements therein, as well as an image control signal (ACT) indicating for each image element whether it belongs to said image area (AA) or not and that said coder means are controlled by said coordinates (BX, BY, PX, PY) and said image control signal (ACT) provided by said control means (Figs. 1, 4).

Claim 15

Image processing system according to claim 13, characterized in that said encoder means (END) include : - an encoder circuit (DPCM) controlled by the coordinates (BX, BY, PX, PY) of said grid blocks and image elements and by said image control signal (ACT); - storage means (FS) storing signals relating to the image elements of image blocks; - means for supplying to said encoder circuit (DPCM); each pair of signals (Y, Yʹ), provided by said converter means (ADC) and by said storage means (FS) respectively and relating to a same image element; - subtracting means (SUB) for providing the absolute value of the difference of said signals of said pair; - summing means (REC) also controlled by said coordinates (BX, BY, PX, PY) and said image control signal (ACT); - gating means (MUX2) coupling the output signal of said subtracting means (SUB) and a fixed value (PV) to said summing means, said gating means (MUX2) being controlled by said image control signal (ACT) in such a way that said absolute value or said fixed value is supplied to said summing means depending on said image control being activated or not respectively, said summing means calculating a sum value for the image elements of each image block; - comparison means (RC) for comparing the sum value provided by said summing means (REC) with a threshold value (TM) and for generating said activated replenishment signal (RCS) only when said sum value exceeds said threshold value (TM), said replenishment signal (RCS) when activated enabling said encoder circuit to encode the signals related to the image elements of said image block, and said replenishment signals (RCS) when deactivated enabling said signals issued from said storage circuit (FS) to be fed back to it (Fig. 5).

Claim 16

Image processing system according to claim 14, characterized in that said encoder circuit is a differential pulse code modulator circuit (DPCM) which calculates an output value for an image element from the previous output value for the preceding image element on the same scanning line of the same scanning field, from the previous ouput value for an homologous image element on the previous scanning line of the same scanning field, and from the previous output value for an homologous image element on the same scanning line of a previous scanning field (Fig. 5).

Claim 17

Phaselocked loop including a clock input signal (CLS) generating circuit (XCL) which is coupled through a variable delay circuit (DL) to a multiplexer circuit (MUXC) which provides a clock output signal (CLL) applied to a first input of a phase detector (CC, CAL, SUB 1/2) whose second input is the input of the loop and whose output on which a phase error signal is generated is coupled to a bidirectional counter (UDC) which controls said multiplexer circuit (MUXC), characterized in that the output of said phase detector (CCC, CAL, SUB 1/2) is coupled to said bidirectional counter (UDC) through latch means (LC) which are controlled by reference signals (SYNC) forming part of a digital bitstream applied to said loop input and which latch each said phase error for a time interval between successive reference signals (SYNC)(Fig. 6).

Claim 18

Phaselocked loop including a clock input signal (CLS) generating circuit (XCL) which is coupled through a variable delay circuit (DL) to a multiplexer circuit (MUXC) which provides a clock output signal (CLL) applied to a first input of a phase detector (CC, CAL, SUB 1/2) whose second input is the input of the loop and whose output on which a phase error signal is generated is coupled to a bidirectional counter (UDC) which controls said multiplexer circuit (MUXC), characterized in that the output of said phase detector (CCC, CAL, SUB 1/2) is coupled to said bidirectional counter (UDC) through latch means (LC) which are controlled by reference signals (SYNC) forming part of a digital bitstream applied to said loop input and which latch each said phase error for a time interval between successive reference signals (SYNC)(Fig. 6).

Claim 19

Phaselocked loop according to clain 16, characterized in that it further includes counter control means (LUC,IC) for controlling said bidirectional counter (UDC) in such a way that it changes said phase error at a predetermined speed (Fig. 6).

Claim 20

Phaselocked loop according to clain 16, characterized in that it further includes counter control means (LUC,IC) for controlling said bidirectional counter (UDC) in such a way that it changes said phase error at a predetermined speed (Fig. 6).

Claim 21

Phaselocked loop according to claim 17, characterized in that said counter control means are programmable (Fig. 6).

Claim 22

Phaselocked loop according to claim 18, characterized in that said counter control means (LUC, IC) include means (LUC) for associating to each phase error a programmable value, and an interval counter (IC) which is stepped by said clock input signal (CLS) and controlled by said programmable value, said counter counting from this value to zero and then issueing an ouput signal which steps said bidirectional counter (UDC) up or down depending on the sign (S) of said phase error which is also provided by said phase detector (Fig. 6).

Claim 23

Image processing system according to claim 13, characterized in that said receiver station (RC) includes a phaselocked loop according to any of the claims 16 to 19 and that said phase detector (CCC, CAL, SUB 1/2) determines said phase error from the comparison of the position of a predetermined element provided by counter means (CCC) driven by said clock output (CLL) of said multiplexer circuit (MUXC) and the position of said predetermined element calculated from a block indicative signal received from said sender station (Fig. 6).

Claim 24

Data processing system with at least one sender station (SC) coupled to a least one receiver station (RC) through a switching network (PSWN), said sender station (SC) including encoder means for encoding data signals prior to applying them to said switching network characterized in that said encoder means (END) provide at their output an encoded bitstream (E1, E2) having a variable bitrate, and that said sender station (SC) further includes means (NIC) to apply said encoded bitstream (E1, E2) directly to said switching network (PSNW)(Fig. 4).

Claim 25

Data processing system with at least one sender station (SC) coupled to a least one receiver station (RC) through a switching network (PSWN), said sender station (SC) including encoder means for encoding data signals prior to applying them to said switching network characterized in that said encoder means (END) provide at their output an encoded bitstream (E1, E2) having a variable bitrate, and that said sender station (SC) further includes means (NIC) to apply said encoded bitstream (E1, E2) directly to said switching network (PSNW)(Fig. 4).

Claim 26

Data processing system according to claim 21, characterized in that said sender (SC) and receiver (RC) stations form part of an image processing system according to any of the claims 1 to 20.