Two port random access memory with column redundancy

Claim 2

Two port random access memory system including a data storage matrix having columns and rows, write means responsive to column address signals for causing data bits to be stored in predetermined logical columns within the data storage matrix, each column address signal having a predetermined physical relationship to at least one column of the data storage matrix, said memory system having transfer means for transferring data bits between a plurality of columns of the data storage matrix and a memory input/output means, said data bits being transferred in parallel to or from the storage matrix serially through said memory input/output means in a sequence determined by the physical order of columns within the data storage matrix, the improvement comprising: a redundant data storage matrix (31) having at least one column; a column redundancy means (30) responsive to at least one predetermined column address signal for storing data bits in a column (R0, R1) of the re­dundant data storage matrix; and control logic means (32), responsive to the column redundancy means (30) and the transfer means (25), for causing data accessed from a redundant column to be presented to the memory input/output means in the sequential column position corresponding to the column address to which the column redundancy means is responsive; whereby the predetermined logical relationship between the column address and the columns in the data storage matrix (11) is preserved when data bits are read from the memory system.

Claim 3

Two port random access memory system as of Claim 1 wherein said control logic means further includes means for causing data bits serially (25) transferred through said memory input/output means (20, 21) from outside said memory to be written to columns of said data storage matrix (11) and said redundant data storage matrix (31) in accordance with said predetermined column address signal, whereby the predetermined logical to physical relationship between the column address and the columns in the data storage matrix is preserved when data bits are serially written in through the memory input/output system.

Claim 4

Two port random access memory system as of Claim 1 wherein said control logic means comprises time division multiplexing means (44) for presenting a data bit accessed from a redundant column to said memory input/output means in a time division manner according to its logical column address.

Claim 5

Two port random access memory system as of Claim 2 wherein said time division multiplexing means (44) includes means (46, 48, 50) for monitoring the identity of the data storage matrix physical columns corresponding the data bits sequentially presented to the memory input/output means during serial read out, and multiplexing means responsive to said monitoring means for preventing said transfer means from presenting to said input/­output means a data bit from a column of the data storage matrix having the predetermined physical relationship with the column address to which the column redundancy means is responsive, and for presenting to said input/output means in its place the data bit from the redundant data storage matrix stored therein in response to said column address to which said column redundancy means is responsive.

Claim 6

Two port random access memory system as of Claim 4 wherein said monitoring means comprises: Counter means (0, 1, 2) for providing a count identifying the physical column of the data storage matrix which stored the data bit being presented to the memory input/output means; code storing means for storing a code corresponding to the count identifying a column of the data storage matrix (11) having the predetermined physical relationship to the column address to which said column redundancy means (62) is responsive, and comparator means responsive to an output of said counter means and an output of said code storing means for detecting when the count in said counter matches a code stored in said code storing means, said multiplexer means including means (40, 42) responsive to the detection of said match for pre­venting read out to said input/output means of a data bit from the physical column of the data storage matrix which corresponds to said code in said code storing means and for reading out to said input/output means a data bit stored in the redundant column addressed by the column address which corresponds to said code stored in said code storing means.

Claim 7

Two port random access memory system as of Claim 5 wherein said transfer means includes a row buffer serial shift register (25) for receiving data bits, the stages of said shift register being electrically connected to predetermined columns of the data storage matrix (11), and wherein said control logic (32) includes at least one latch means (40ʹ) for receiving data bits from said at least one column of said redundant data storage matrix, said multiplexer means (44) being connected to receive the serial output of said row buffer serial shift register and to said latch means.

Claim 8

Two port random access memory system as of Claim 1 wherein said transfer means comprises a row buffer serial shift register transferring data bits to or from columns of said data storage matrix, the stages of said shift register being electrically connected to predetermined columns of the data storage matrix; and said control logic means comprises, at least one latch means (40ʹ) for storing a data bit having said predetermined column address to which said column redundancy means is responsive, gating means (T4-T8) for selectively causing data bits sequentially trans­ ferred through said shift register to by-pass the register stage connected to the column of the data storage matrix having the predetermined physical relationship to the column address to which the column redundancy means is responsive and for causing the data bits to instead pass through said latch means, said latch means appearing to said data bits to be in the physical position of said by-passed shift register stage, and decoder means responsive to the column address to which said column redundancy means is responsive for enabling said gating means.

Claim 9

Two port random access memory system including a data storage matrix having columns and rows, write means responsive to column address signals for causing data bits to be stored in predetermined logical columns within data storage matrix, each column address defining a predeter­mined logical to physical relationship between the logical column defined by the column address and a physical column of the data storage matrix, said memory system having transfer means for trans­ferring data bits between a plurality of physical columns of said data storage matrix and a data input/­output means, said data bits being transferred in parallel to or from said data storage matrix and serially through said data input/output means in a sequence corresponding to the logical column order determined by said column address signals, the improvement comprising: a redundant data storage matrix (31) having at least one column; a column redundancy means (30) responsive to at least one predetermined column address signal for storing data bits in a column of the redundant data storage matrix; and for signalling that column redundancy has been selected; and control logic means (32), responsive to the column redundancy means and said transfer means, for causing data bits sequentially transferred through said data input/output means and having respective predetermined corresponding logical column posi­tions to maintain their respective logical column positions during both reading and writing of data bits from and to said storage matrix when column redundancy has been selected.

Claim 10

Two port random access memory system including a data storage matrix having columns and rows, write means responsive to column address signals for causing data bits to be stored in predetermined logical columns within data storage matrix, each column address defining a predeter­mined logical to physical relationship between the logical column defined by the column address and a physical column of the data storage matrix, said memory system having transfer means for trans­ferring data bits between a plurality of physical columns of said data storage matrix and a data input/­output means, said data bits being transferred in parallel to or from said data storage matrix and serially through said data input/output means in a sequence corresponding to the logical column order determined by said column address signals, the improvement comprising: a redundant data storage matrix (31) having at least one column; a column redundancy means (30) responsive to at least one predetermined column address signal for storing data bits in a column of the redundant data storage matrix; and for signalling that column redundancy has been selected; and control logic means (32), responsive to the column redundancy means and said transfer means, for causing data bits sequentially transferred through said data input/output means and having respective predetermined corresponding logical column posi­tions to maintain their respective logical column positions during both reading and writing of data bits from and to said storage matrix when column redundancy has been selected.