Patent EP0245765A2 successfully refreshed from Google Patents.
EP0245765A2
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Data transfer control system
Assignee: Mitsubishi Electric Corp
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Filing: 1987-05-06
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Granted: —
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Expires: 2007-05-06
Abstract
Abstract The timings, at which data is supplied to and from a buffer, in which data to be transmitted or received is temporarily stored, is controlled by a controller to eliminate underflow even with token excursion time variations. When establishing synchronization between nodes, synchronizing clock phase data are exchanged between the nodes to obtain mutual synchronization. This synchronizing system permits circuit switching using a token ring system network.
Inventors
- 👤 Masahiro Mitsubishi Denki K.K. Matsumoto
- 👤 Akira Mitsubishi Denki K.K. Watanabe
- 👤 Kazuo Mitsubishi Denki K.K. Ohhashi
- 👤 Minoru Mitsubishi Denki K.K. Itao
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 18:07
CPC Classifications
H; H04; H04L; H04L47/00; H04L47/10; H04L47/28; H04L12/00; H04L12/28; H04L12/42; H04L12/422; H04L12/427; H04L12/433; H04L47/13; H04L47/30
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
132 words
A data transfer control system for performing data transfer control using a packet multiplex network of a token ring system, in which the upper limit of the transmission waiting time of each node is guaranteed, each node serving to pass data from an associated terminal to said network and including a controller for controlling the input to and output from a data buffer for temporarily storing said data therein and basic clock generating means for generating a basic clock, said controller serving to control the timing of transmission of data to said network to produce a constant delay time, the phase data of a clock generated from said basic clock generating means being transmitted using a packet to a different node to obtain synchronization of the basic clock in said different node.
Claim 2
Dependent Claim
132 words
A data transfer control system for performing data transfer control using a packet multiplex network of a token ring system, in which the upper limit of the transmission waiting time of each node is guaranteed, each node serving to pass data from an associated terminal to said network and including a controller for controlling the input to and output from a data buffer for temporarily storing said data therein and basic clock generating means for generating a basic clock, said controller serving to control the timing of transmission of data to said network to produce a constant delay time, the phase data of a clock generated from said basic clock generating means being transmitted using a packet to a different node to obtain synchronization of the basic clock in said different node.
Claim 3
Dependent Claim
25 words
The data transfer control system according to claim 1, wherein said constant delay time is double the maximum token excursion time through the token ring.
Claim 4
Dependent Claim
32 words
The data transfer control system according to claim 1, wherein the transmission of data from a transmitting side data buffer to the ring transmission line is started after a predetermined delay time.
Claim 5
Dependent Claim
30 words
The data transfer control system according to claim 1, wherein the transmission of data from a receiving side data buffer to the terminal is started after a predetermined delay time.
Claim 6
Dependent Claim
49 words
The data transfer control system according to claim 1, wherein the transfer of data from the transmitting side data buffer to the ring transmission line and transfer of data from the receiving side data buffer to the terminal are started after delay times constituting altogether a predetermined delay time.
Claim 7
Dependent Claim
117 words
The data transfer control system according to claim 1, wherein a node functioning as a synchronization master when establishing clock synchronization between nodes includes basic clock generation means for supplying a basic clock to an associated node and generating phase data of said basic clock as digital data consisting of predetermined bits, said digital phase data being sent out as a packet to the network, a node functioning as a synchronization slave includes basic clock reproducing means functioning with said digital phase data received through the network as a goal of control to reproduce a clock synchronized to said basic clock, and synchronization between particular nodes is established by supplying the reproduced clock to the associated terminal.
Claim 8
Dependent Claim
23 words
The data transfer control system according to claim 1, wherein each node includes both basic clock generating means and basic clock reproducing means.
Claim 9
Dependent Claim
23 words
The data transfer control system according to claim 1, wherein each node includes either basic clock generating means or basic clock reproducing means.
Claim 10
Dependent Claim
51 words
The data transfer control system according to claim 1, wherein said basic clock generating means includes an oscillator and a frequency divider for frequency dividing the frequency of the output of said oscillator and also providing digital values of individual frequency division stages to form phase data of said basic clock.
Claim 11
Dependent Claim
52 words
The data transfer control system according to claim 1, wherein said basic clock generating means includes a frequency divider for frequency dividing an externally supplied clock to generate a basic clock supplied to the terminal while providing digital values of individual frequency division stages to form phase data of said basic clock.
Claim 12
Dependent Claim
144 words
The data transfer control system according to claim 1, wherein said basic clock reproducing means , includes a master phase register for holding digital phase data received through the network, a voltage-controlled oscillator with the oscillation frequency thereof controllable according to a control voltage, a frequency divider for frequency dividing the output frequency of said oscillator to generate a clock to be supplied to the terminal while also providing digital values of individual frequency division stages to generate phase data of said clock, a slave phase register for holding digital phase data provided from said frequency divider, a subtracter for performing subtraction of the outputs of said master and slave phase registers to provide the phase difference, and a digital-to-analog converter for converting the digital output of said subtracter into an analog voltage to be supplied as a control voltage of said voltage-controlled oscillator.
Claim 13
Dependent Claim
74 words
The data transfer control system according to claim 1, wherein said basic clock generating means includes a variable frequency divider capable of clock division ratio variation and an operation circuit for controlling the frequency division ratio of said variable frequency divider through comparison of the master phase received through the network and slave phase generated in said variable frequency divider in the receiving node, thus permitting said slave phase to follow said master phase.
References Cited (Backward Citations)
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