Raster display controller with variable spatial resolution and pixel data depth

Claim 2

A display control apparatus for storing image data representing an image to be displayed and for providing a stream of display control data to a display means for displaying said image, said display control apparatus comprising: storage means (FRAME BUFFER) for storing said image data; reading means (LINE COUNTER) for reading said image data out of said storage means; translation means (VLT, DAC) for translating said image data into said display control data; a plurality of shift register means (SHRO-SHR7) for receiving the image data from said storage means and for providing said image data to said translation means when enabled; and characterized by: control means (MODR, NAND1, NAND2, CLR, SHIFT) for selectively enabling and disabling different ones of said shift register means in accordance with a desired image resolution.

Claim 3

A display control apparatus as defined in claim 1, wherein said storage means comprises a memory having I lines and J columns of storage locations each for storing a pixel data value, with each storage location having K bits, and said shift register means comprise K shift registers each receiving a different one of said bits from each pixel data value read out of said storage means, and wherein said display control apparatus is capable of operating in a first resolution mode wherein all of said shift registers are enabled at one time, and at least one second resolution mode wherein at most L of said shift registers are enabled at one time, where L<K and preferably L divides K.

Claim 4

A display control apparatus as defined in any previous claim, wherein said display control apparatus is capable of operating in a plurality of second resolution modes.

Claim 5

A display control apparatus as defined in claim 3, wherein said plurality of second resolution modes include different horizontal resolutions.

Claim 6

A display control apparatus as defined in claim 3 or 4, wherein said plurality of second resolution modes include different vertical resolutions.

Claim 7

A display control apparatus as defined in any previous claim, wherein said reading means comprises address means (LCNT) for generating a multi-bit cyclical signal, with M bits being provided to said storage means as an address signal for reading out said image data and at least one additional bit (LC<9>) - designating shift registers to be enabled during operation in said second resolution mode.

Claim 8

A display control apparatus as defined in claim 6, wherein said control means includes mode designation means (MODR) for providing a mode signal indicating the desired resolution mode, and logic means (NAND1, NAND2, SG MUX, SH MUX) responsive to said mode signal and to the value of said at least one additional bit for selectively enabling and disabling said shift registers.

Claim 9

A display control apparatus as defined in claim 2, wherein said translation means comprises at least

Claim 10

one memory (VLT) addressed by the collective outputs of said plurality of shift registers, said at least one memory, in said second resolution mode, storing display control values corresponding to the address values represented by the L shift registers which are enabled at one time, whereby identical display control values are stored at different locations (Table 1) in said at least one memory.

Claim 11

one memory (VLT) addressed by the collective outputs of said plurality of shift registers, said at least one memory, in said second resolution mode, storing display control values corresponding to the address values represented by the L shift registers which are enabled at one time, whereby identical display control values are stored at different locations (Table 1) in said at least one memory.

Claim 12

A display control apparatus as defined in claim 1, wherein: said storage means comprises a buffer memory having I lines and J columns of storage locations each for storing a pixel data value, with each storage location having K bits, said buffer memory having separately controllable write enable terminals ( WE) corresponding to each of said K bits for enabling the writing of data into a respective bit position in accordance with write enable signals, and data Input/Output (I/O) ports for providing data to and from said buffer; said display control apparatus is capable of operating in a first resolution mode in which all shift registers are enabled at one time and a second resolution mode in which less than all of said shift registers are enabled at one time, said reading means comprises address means for generating a multi-bit cyclical signal, with M bits being provided to said storage means as an address signal for reading out said image data and at least one additional bit for designating shift registers to be enabled during operation in said second resolution mode, and means for providing a read signal (FB RD) designating a read operation; said display control device further includes means for providing a mode signal (MODE) designating a desired resolution mode, means for providing a write signal (FB WR) designating a write operation, transceiver means (T1-T3) coupled between said data I/0 ports and a host processor data bus for passing data in a direction in accordance with a direction control signal at their control (D) terminals; logic means (NANDS-NAND6) responsive to said mode signal, said write signal and the value of said additional bit for providing said write enable signals, and logic means (NAND3-NAND4) responsive to said mode signal, said read signal and the value of said additional bit for providing said direction control signals.

Claim 13

A display control apparatus as defined in claim 9, wherein said transceiver means comprises a first transceiver (T1) coupled to a first plurality of said data I/0 ports and to a first plurality of bit positions of said host processor data bus and receiving a first direction control (NAND3) signal, a second transceiver (T3) coupled between a second plurality of said data 1/0 ports and said first plurality of bit positions of said host processor data bus and receiving a second direction control (NAND4) signal, a third transceiver (T2) coupled between said second plurality of data I/0 ports and a second plurality of bit positions of said host processor data bus and receiving said second direction control signal, and further logic means (INV2) responsive to said mode signal for selectively enabling only one of said second and third transceivers.

Claim 14

A display control apparatus as defined in claim 1, wherein: said reading means comprises a line counter (LCNT) for counting line signals and providing at least a portion of its output as a line count address to said storage means (FRAME BUFFER), a pixel counter (PCNT) for counting pixel signals and providing at least a portion of its output as a pixel count address to said storage and/or said display means, and a first multiplexer means (SG MUX) for selectively providing any one of a plurality of pixel counter outputs as line count increment signals to said line counter in accordance with a mode (MODR) signal; and said control means comprises a first register (CLR) for storing clear data representing shift registers to be enabled, a control shift register (SHIFT) for receiving said clear data and serially shifting said clear data in accordance with a shift signal (SH), the contents of said control shift register then being provided in parallel as enabling signals to said plurality of shift registers, and second multiplexer means (SH MUX) responsive to said mode signal for providing selected outputs from said pixel and line counters to said control shift register as said shift signal.