Parallel computer system capable of asynchronous data transmission

Claim 2

A parallel computer system comprising: a plurality of processors (2) mutually connected and operable in parallel; and a host processor (7) connected to said plurality of processors (2) for loading each processor with one of plural parts of a program which parts are formed so as to communi­cate mutually during execution thereof; each processor (2) comprising: receive means (5) for receiving plural sets of a data signal and a data identification code predetermined for the data signal; memory means (21) for holding the received sets; and processing means (3) connected to said memory means (21) for executing instructions, including first means (61, 10) responsive to a first instruction for informing said memory means (21) of a data identification code designated by the first instruction; and said memory means (21) including: means responsive to the informed data identification code for detecting a specific set of a data signal and a data identification code which is the same as the informed data identification code and for sending the data signal included in the detected specific set to said processing means (3).

Claim 3

The computer system of claim 1, wherein said processing means (3) further includes second means (61, 10) responsive to a second instruction for generating a set of a data signal designated thereby and a data identification code designated thereby, and wherein said processor (2) further includes send means (4) connected to said processing means (3) for sending the generated set of the data signal and the data identifi­cation code.

Claim 4

The computer system of claim 1 or 2, wherein said memory means (21) is comprised of associative memory means for holding a data identification code received together with a corresponding data signal as an associative key to the data signal.

Claim 5

The computer system of any of claims 1 to 3, further com­prising: another memory means (42) connected to said receive means (5) and processing means (3) for holding the informed data identification code when the specific set is not detected and for detecting receipt by said receive means of a data signal accompanied by a data identification code which is the same as one of the codes held by said another memory means (42), so as to inform said processing means (3) of the receipt.

Claim 6

A parallel computer system comprising: a plurality of processors (2) mutually connected and operable in parallel, and a host processor (7) connected to said plurality of pro­cessors (2) for loading each processor with one of plural parts of a program which parts are formed so as to communicate mutually during execution thereof; each processor (2) comprising: storage means (6, 10) for holding instructions to be executed thereby and data signals; instruction means (60, 61) connected to said storage means (6, 10) for putting the instructions into an execution state according to a predetermined order; operation means (70) connected to said storage means (6, 10) and said instruction means (60, 61) and responsive to a first one of the instructions for performing an operation on a data signal held at a location of said storage means (6, 10) designated by the first instruction; send means (4) connected to said instruction means (60, 61) and said storage means (6, 10) and responsive to a second one of the instructions for sending to one of other processors (2) a data signal together with a data identification code designated by the second instruction; and receive means (20, 21) for receiving and holding data signals sent from other processors (2) each with a data iden­tification code and responsive to execution of a third one of the instructions for detecting the presence of a specific data signal accompanied with a data identification code desig­nated by the third instruction, so as to transfer the specific data signal to said storage means (6, 10) when the data signal is present and so as to provide a control signal to prohibit said instruction means (60, 61) to execute succeeding in­structions which are to be after the third instruction, when the data signal is not present, so as to transfer the specific data signal to said storage means (6, 10).

Claim 7

A parallel computer system comprising: a plurality of processors (2) mutually connected and operable in parallel, and a host processor (7) connected to said plurality of pro­cessors (2) for loading each processor with one of plural parts of a program which parts are formed so as to communicate mutually during execution thereof; each processor (2) comprising: storage means (6, 10) for holding instructions to be executed thereby and data signals; instruction means (60, 61) connected to said storage means (6, 10) for putting the instructions into an execution state according to a predetermined order; operation means (70) connected to said storage means (6, 10) and said instruction means (60, 61) and responsive to a first one of the instructions for performing an operation on a data signal held at a location of said storage means (6, 10) designated by the first instruction; send means (4) connected to said instruction means (60, 61) and said storage means (6, 10) and responsive to a second one of the instructions for sending to one of other processors (2) a data signal together with a data identification code designated by the second instruction; and receive means (20, 21) for receiving and holding data signals sent from other processors (2) each with a data iden­tification code and responsive to execution of a third one of the instructions for detecting the presence of a specific data signal accompanied with a data identification code desig­nated by the third instruction, so as to transfer the specific data signal to said storage means (6, 10) when the data signal is present and so as to provide a control signal to prohibit said instruction means (60, 61) to execute succeeding in­structions which are to be after the third instruction, when the data signal is not present, so as to transfer the specific data signal to said storage means (6, 10).