Patent EP0264893A2 successfully refreshed from Google Patents.
EP0264893A2
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EP
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Semiconductor memory
Assignee: NTT Inc
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Filing: 1987-10-19
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Granted: —
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Expires: 2007-10-19
Abstract
Abstract A semiconductor memory includes a plurality of memory cells which are arranged in a matrix and respectively store data, a plurality of bit lines and a plurality of word lines, connected to the plurality of memory cells, for performing read/write access of data to the memory cells, and a test circuit. In the test circuit, an external terminal sends test data and expected value data written in the memory cells. A simultaneous write circuit simultaneously writes the test data from the external terminal in the plurality of memory cells connected to a selected word line. A simultaneous comparison circuit simultaneously compares the test data written in the plurality of memory cells connected to the selected word line with the expected value data supplied from the external terminal in correspondence with the selected word line.
Inventors
- 👤 Tsuneo Nippon Telegraph & Teleph. Corp. Matsumura
- 👤 Tsuneo Nippon Telegraph & Teleph. Corp. Mano
- 👤 Junzo Nippon Telegraph & Teleph. Corp. Yamada
- 👤 Junichi Nippon Telegraph & Tel. Corp. Inoue
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 11:00
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
148 words
A semiconductor memory comprising: a plurality of memory cells which are arranged in a matrix and respectively store data; a plurality of bit lines and a plurality of word lines, connected to said plurality of memory cells, for performing read/write access of data to said memory cells; and a test circuit, said test circuit comprising external terminal means for sending test data and expected value data written in said memory cells, simultaneous write means for simultaneously writing the test data from said external terminal means in said plurality of memory cells connected to a selected word line, and simultaneous comparison means for simultaneously comparing the test data written in said plurality of memory cells connected to said selected word line with the expected value data supplied from said external terminal means in correspondence with the selected word line, whereby a test of said memory cells can be performed.
Claim 2
Dependent Claim
148 words
A semiconductor memory comprising: a plurality of memory cells which are arranged in a matrix and respectively store data; a plurality of bit lines and a plurality of word lines, connected to said plurality of memory cells, for performing read/write access of data to said memory cells; and a test circuit, said test circuit comprising external terminal means for sending test data and expected value data written in said memory cells, simultaneous write means for simultaneously writing the test data from said external terminal means in said plurality of memory cells connected to a selected word line, and simultaneous comparison means for simultaneously comparing the test data written in said plurality of memory cells connected to said selected word line with the expected value data supplied from said external terminal means in correspondence with the selected word line, whereby a test of said memory cells can be performed.
Claim 3
Dependent Claim
32 words
A memory according to claim 1, wherein the test data and the expected value data sent from said test circuit are constituted by a 1-bit signal of "0" or "1" " each.
Claim 4
Dependent Claim
22 words
A memory according to claim 1, wherein the expected value data is the test data or inverted data of the test data.
Claim 5
Dependent Claim
23 words
A memory according to claim 1, wherein said bit lines have a folded bit line connection arrangement with respect to said memory cells.
Claim 6
Dependent Claim
23 words
A memory according to claim 1, wherein said bit lines have an open bit line connection arrangement with respect to said memory cells.
Claim 7
Dependent Claim
22 words
A memory according to claim 1, wherein sense circuits connected to said bit lines are arranged at two sides of the matrix.
Claim 8
Dependent Claim
69 words
A memory according to claim 1, wherein said external terminal means also has a function of a data input/output terminal, and further comprises: a test mode setting signal generator for detecting a level transition timing of a fundamental clock and sending a test mode setting signal; and switch means, said switch means connecting said external terminal means to said test circuit upon reception of the test mode setting signal.
Claim 9
Dependent Claim
46 words
A memory according to claim 7, wherein said switch means switches said external terminal means . from a data transmission system for said memory cells to said test circuit upon reception of the test mode setting signal and a write control signal of the test data.
Claim 10
Dependent Claim
32 words
A memory according to claim 7, wherein the fundamental clock comprises a row control clock RAS, a column control clock CAS, and a write control clock WE for said memory cell matrix.
Claim 11
Dependent Claim
18 words
A memory according to claim 7, further comprising latch means between said switch means and said test circuit.
Claim 12
Dependent Claim
17 words
A memory according to claim 1, wherein said external terminal means includes independent input and output circuits.
Claim 13
Dependent Claim
16 words
A memory according to claim 1, wherein said external terminal means includes an input/output common circuit.
Claim 14
Dependent Claim
31 words
A memory according to claim 1, wherein said memory cells arranged in the matrix comprise a plurality of main memory cells and a plurality of supplementary memory cells for defect remedy.
Claim 15
Dependent Claim
40 words
A memory according to claim 13, wherein said simultaneous write means simultaneously writes the test data in the plurality of main memory cells and the plurality of supplementary memory cells, both of which are connected to a selected word line.
Claim 16
Dependent Claim
30 words
A memory according to claim 13, wherein said simultaneous write means simultaneously writes the test data in the plurality of supplementary memory cells connected to a selected supplementary word line.
Claim 17
Dependent Claim
35 words
A memory according to claim 13, wherein said test circuit comprises switching control means for disconnecting a defective memory cell from said simultaneous comparison means and connecting the supplementary memory cell to the corresponding portion.
Claim 18
Dependent Claim
28 words
A memory according to claim 16, wherein said switching control means comprises means for disconnecting a comparator of said simultaneous comparison means corresponding to the defective memory cell.
Claim 19
Dependent Claim
29 words
A memory according to claim 16, wherein said switching control means comprises a storage element, said storage element being arranged to change its storage value when a defect occurs.
Claim 20
Dependent Claim
19 words
A memory according to claim 18, wherein the storage value corresponds to an address of the defective memory cell.
Claim 21
Dependent Claim
69 words
A memory according to claim 13, wherein said external terminal means also has a function of a data input/output terminal, and further comprises: a test mode setting signal generator for detecting a level transition timing of a fundamental clock and sending a test mode setting signal; and switch means, said switch means connecting said external terminal means to said test circuit upon reception of the test mode setting signal.
Claim 22
Dependent Claim
18 words
A memory according to claim 20, further comprising latch means between said switch means and said test circuit.
Claim 23
Dependent Claim
17 words
A memory according to claim 20, wherein said external terminal means includes independent input and output circuits.
Claim 24
Dependent Claim
16 words
A memory according to claim 20, wherein said external terminal means includes a common input/output circuit.
Claim 25
Independent Claim
112 words
A method of testing a semiconductor memory comprising: using a semiconductor memory comprising a plurality of memory cells arranged in a matrix, a peripheral circuit for selectively writing or reading out data in or from selected ones of said memory cells, and a test circuit; sequentially testing predetermined portions by said test circuit in a predetermined order and stopping subsequent tests when a defect is detected; and simultaneously writing test data in predetermined memory cells connected to bit lines intersecting one word line when said memory cells serve as objects to be tested, and thereafter, comparing readout data with expected value data to check the memory cell connected to said word line.
Claim 26
Independent Claim
112 words
A method of testing a semiconductor memory comprising: using a semiconductor memory comprising a plurality of memory cells arranged in a matrix, a peripheral circuit for selectively writing or reading out data in or from selected ones of said memory cells, and a test circuit; sequentially testing predetermined portions by said test circuit in a predetermined order and stopping subsequent tests when a defect is detected; and simultaneously writing test data in predetermined memory cells connected to bit lines intersecting one word line when said memory cells serve as objects to be tested, and thereafter, comparing readout data with expected value data to check the memory cell connected to said word line.
Claim 27
Dependent Claim
20 words
A method according to claim 24, wherein said predetermined memory cells are all memory cells connected to one word line.
Claim 28
Dependent Claim
28 words
A method according to claim 24, wherein said predetermined memory cells are all memory cells in a divided section of the memory cells connected to one word line.
Claim 29
Dependent Claim
31 words
A method according to claim 24, wherein in the test, said peripheral circuit has a highest priority order, and circuits other than said peripheral circuit has the second highest priority order.
Claim 30
Dependent Claim
29 words
A method according to claim 24, wherein in the test, said peripheral circuit is tested first, said test circuit is tested second, and said memory cells are tested last.
Claim 31
Dependent Claim
37 words
A method according to claim 24, wherein the test of said peripheral circuit is performed for a portion corresponding to a memory cell line along at least one diagonal line of said memory cells on the matrix.
Claim 32
Dependent Claim
66 words
A method according to claim 24, wherein the test of said peripheral circuit is performed for a portion corresponding to a memory cell line along at least one diagonal line, a portion corresponding to a memory cell line along at least one word line, and a portion corresponding to a memory cell line along at least one bit line, of said memory cells on the matrix.
Claim 33
Dependent Claim
52 words
A method according to claim 24, wherein the test of said peripheral circuit is performed for a portion corresponding to a memory cell line along at least one word line, and a portion corresponding to a memory cell line along at least one bit line, of said memory cells on the matrix.
Claim 34
Dependent Claim
15 words
A method according to claim 24, wherein data for the test is externally input data.
Claim 35
Dependent Claim
28 words
A method according to claim 24, wherein data for the test is data stored in an internal memory element, and is externally selected to perform a corresponding test.
Claim 36
Dependent Claim
37 words
A method according to claim 24, wherein the test is divided into a plurality of steps depending on portions to be tested, and a result of each test is checked after each step of test is completed.
Claim 37
Dependent Claim
37 words
A method according to claim 24, wherein the test is divided into a plurality of steps depending on portions to be tested. and a result of each test is checked during each step of test is completed.
Claim 38
Independent Claim
154 words
A method of testing a semiconductor memory comprising: using a semiconductor memory comprising a plurality of main memory cells for storing data, a plurality of supplementary memory cells for defect remedy, a peripheral circuit for selectively writing or reading out data in or from selected ones of said memory cells, and a test circuit; sequentially testing predetermined portions by said test circuit in a predetermined order and inhibiting subsequent tests when the defect remedy cannot be performed by substituting a defective memory cell with the supplementary memory cell; and simultaneously writing test data in predetermined memory cells connected to bit lines and supplementary bit lines intersecting one word line or one supplementary word line when said main memory cells and said supplementary memory cells serve as objects to be tested, and thereafter, comparing readout data with expected value data to check the memory cells connected to said word line or the supplementary word line.
Claim 39
Independent Claim
154 words
A method of testing a semiconductor memory comprising: using a semiconductor memory comprising a plurality of main memory cells for storing data, a plurality of supplementary memory cells for defect remedy, a peripheral circuit for selectively writing or reading out data in or from selected ones of said memory cells, and a test circuit; sequentially testing predetermined portions by said test circuit in a predetermined order and inhibiting subsequent tests when the defect remedy cannot be performed by substituting a defective memory cell with the supplementary memory cell; and simultaneously writing test data in predetermined memory cells connected to bit lines and supplementary bit lines intersecting one word line or one supplementary word line when said main memory cells and said supplementary memory cells serve as objects to be tested, and thereafter, comparing readout data with expected value data to check the memory cells connected to said word line or the supplementary word line.
Claim 40
Dependent Claim
40 words
A method according to claim 36, wherein said predetermined memory cells are all the main memory cells and all the supplementary memory cells connected to one word line or all the supplementary memory cells connected to one supplementary word line.
Claim 41
Dependent Claim
67 words
A method according to claim 36, wherein said predetermined memory cells are all the main memory cells and all the supplementary memory cells in a divided section or all the supplementary memory cells in the divided section, of the main memory cells and the supplementary memory cells, both of which are connected to one word line, or the supplementary memory cells connected to one supplementary word line.
Claim 42
Dependent Claim
31 words
A method according to claim 36, wherein in the test, said peripheral circuit has a highest priority order, and circuits other than said peripheral circuit has the second highest priority order.
Claim 43
Dependent Claim
29 words
A method according to claim 36, wherein in the test, said peripheral circuit is tested first, said test circuit is tested second, and said memory cells are tested last.
Claim 44
Dependent Claim
37 words
A method according to claim 36, wherein the test of said peripheral circuit is performed for a portion corresponding to a memory cell line along at least one diagonal line of said memory cells on the matrix.
Claim 45
Dependent Claim
66 words
A method according to claim 36, wherein the test of said peripheral circuit is performed for a portion corresponding to a memory cell line along at least one diagonal line, a portion corresponding to a memory cell line along at least one word line, and a portion corresponding to a memory cell line along at least one bit line, of said memory cells on the matrix.
Claim 46
Dependent Claim
56 words
A method according to claim 36, wherein the test of said peripheral circuit is performed for a portion corresponding to a portion corresponding to a memory cell line along at least one word line, and a portion corresponding to a memory cell line along at least one bit line, of said memory cells on the matrix.
References Cited (Backward Citations)
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