Patent EP0276981A2 successfully refreshed from Google Patents.
EP0276981A2
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Semiconductor integrated circuit device and method of producing same
Assignee: Fujitsu Ltd
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Filing: 1988-01-26
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Granted: —
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Expires: 2008-01-26
Abstract
Abstract A semiconductor integrated circuit device comprises a negative differential resistance element (11, 12, 13), such as an RHET or an RBT, and a field effect transistor (14, 15), such as an SBFET or a heterojunction type FET, which are formed on the same semiconductor substrate (1), a base layer of the negative differential resistance element and a channel layer of the field effect transistor being formed on the same epitaxial layer, and the same conductive material is used to simultaneously form an emitter electrode (11) and a gate (14). A monolithic integration of both the element and transistor can be achieved both rationally and easily.
Inventors
- 👤 Toshihiko Mori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 05:31
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/05; B; B82; B82Y; B82Y10/00; H10D84/0107
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
49 words
A semiconductor integrated circuit device comprising a negataive differential resistance element and a field effect transistor which are formed on the same semiconductor substrate, a base layer of said negative differential resistance element and a channel layer of said field effect transistor being formed as a same epitaxial layer.
Claim 2
Dependent Claim
49 words
A semiconductor integrated circuit device comprising a negataive differential resistance element and a field effect transistor which are formed on the same semiconductor substrate, a base layer of said negative differential resistance element and a channel layer of said field effect transistor being formed as a same epitaxial layer.
Claim 3
Dependent Claim
31 words
A device according to claim 1, wherein said negative differential resistance element is a resonant tunneling hot electron transistor and said field effect transistor is a Schottky-barrier type field effect transistor.
Claim 4
Dependent Claim
31 words
A device according to claim 1, wherein said negative differential resistance element is a resonant tunneling hot electron transistor and said field effect transistor is a heterojunction type field effect transistor.
Claim 5
Dependent Claim
30 words
A device according to claim 1, wherein said negative differential resistance element is a resonant tunneling bipolar transistor and said field effect transistor is a Schottky-barrier type field effect transistor.
Claim 6
Independent Claim
175 words
A method of producing a semiconductor integrated circuit device composed of a negative differential resistance element and a field effect transistor which are formed on the same semiconductor substrate, a base layer of said negative differential resistance element and a channel layer of said field effect transistor being formed as the same epitaxial layer, said method comprising the steps of: epitaxially growing semiconductor layers on said semiconductor substrate; selectively removing portions of said semiconductor layers; using the same conductive material to simultaneously form an emitter electrode of said negative differential resistance element coming into ohmic contact with the top layer of said semiconductor layers in the unremoved region and a gate electrode of said field effect transistor coming into Schottky contact with one of said semiconductor layers exposed by said selective removal; and using another same conductive material to simultaneously form a base electrode of said negative differential resistance element and a source electrode and a drain electrode of said field effect transistor coming into ohmic contact with said exposed layer of said semiconductor layers.
Claim 7
Independent Claim
175 words
A method of producing a semiconductor integrated circuit device composed of a negative differential resistance element and a field effect transistor which are formed on the same semiconductor substrate, a base layer of said negative differential resistance element and a channel layer of said field effect transistor being formed as the same epitaxial layer, said method comprising the steps of: epitaxially growing semiconductor layers on said semiconductor substrate; selectively removing portions of said semiconductor layers; using the same conductive material to simultaneously form an emitter electrode of said negative differential resistance element coming into ohmic contact with the top layer of said semiconductor layers in the unremoved region and a gate electrode of said field effect transistor coming into Schottky contact with one of said semiconductor layers exposed by said selective removal; and using another same conductive material to simultaneously form a base electrode of said negative differential resistance element and a source electrode and a drain electrode of said field effect transistor coming into ohmic contact with said exposed layer of said semiconductor layers.
Claim 8
Dependent Claim
108 words
A method according to claim 5, wherein a semiinsulating GaAs substrate is used as said semiconductor substrate, an n-GaAs collector layer, an i-AlGaAs collector barrier layer, an n-GaAs base layer, an i-AlGaAs/i-GaAs/i-AlGaAs multilayer emitter barrier layer having a resonant tunneling barrier structure, an n-GaAs emitter layer and an n-InGaAs emitter contact layer are successively epitaxially grown on the substrate as said semiconductor layers for said negative differential resistance element and for said field effect transistor, the n-InGaAs emitter contact layer and a portion of the n-GaAs emitter layer are selectively removed by etching, and said gate electrode is then formed on the remaining portion of said emitter layer.
Claim 9
Dependent Claim
108 words
A method according to claim 5, wherein a semiinsulating GaAs substrate is used as said semiconductor substrate, an n-GaAs collector layer, an n-AlGaAs collector barrier layer, an i-GaAs base layer, an i-AlGaAs/i-GaAs/i-AlGaAs multilayer emitter barrier layer having a resonant tunneling barrier structure, an n-GaAs emitter layer and an n-InGaAs emitter contact layer are successively epitaxially grown on the substrate as said semiconductor layers for said negative differential resistance element, and for said field effect transistor, the n-InGaAs emitter contact layer and a portion of the n-GaAs emitter layer are selectively removed by etching, and said gate electrode is then formed on the remaining portion of said emitter layer.
Claim 10
Dependent Claim
102 words
A method according to claim 5, wherein a semiinsulating GaAs substrate is used as said semiconductor substrate, an n-GaAs collector layer, a p-GaAs base layer, an i-AlGaAs/i-GaAs/i-AlGaAs multilayer emitter barrier layer having a resonant tunneling barrier structure, an n-AlGaAs emitter layer and an n-InGaAs emitter contact layer are successively epitaxially grown on the substrate as said semiconductor layers for said negative differential resistance element and for said field effect transistor, the n-InGaAs emitter contact layer, the n-GaAs emitter layer and the multilayer emitter barrier layer are selectively removed by etching, and said gate electrode is then formed on the p-GaAs base layer.
Claim 11
Independent Claim
154 words
A method of producing a semiconductor integrated circuit device composed of a negative differential resistance element and a field effect transistor which are formed on the same semiconductor substrate, a base layer of said negative differential resistance element and a channel layer of said field effect transistor being formed as the same epitaxial layer, said method comprising the steps of: epitaxially growing semiconductor layers on said semiconductor substrate; selectively removing portions of said semiconductor layers; using the same conductive material to simultaneously form an emitter electrode of said negative differential resistance element coming into ohmic contact with the top layer of said semiconductor layers in the unremoved region and a gate electrode of said field effect transistor coming into Schottky contact with one of said semiconductor layers exposed by said selective removal; and forming a drain electrode of said field effect transistor coming into ohmic contact with said exposed layer of said semiconductor layers.
Claim 12
Independent Claim
154 words
A method of producing a semiconductor integrated circuit device composed of a negative differential resistance element and a field effect transistor which are formed on the same semiconductor substrate, a base layer of said negative differential resistance element and a channel layer of said field effect transistor being formed as the same epitaxial layer, said method comprising the steps of: epitaxially growing semiconductor layers on said semiconductor substrate; selectively removing portions of said semiconductor layers; using the same conductive material to simultaneously form an emitter electrode of said negative differential resistance element coming into ohmic contact with the top layer of said semiconductor layers in the unremoved region and a gate electrode of said field effect transistor coming into Schottky contact with one of said semiconductor layers exposed by said selective removal; and forming a drain electrode of said field effect transistor coming into ohmic contact with said exposed layer of said semiconductor layers.
References Cited (Backward Citations)
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