Patent US6702607B2 successfully refreshed from Google Patents.
Patent EP0278619A1 successfully refreshed from Google Patents.
EP0278619A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Integrated bipolar and CMOS transistor fabrication process
Assignee: Texas Instruments Inc
•
Filing: 1988-01-25
•
Granted: —
•
Expires: 2008-01-25
Abstract
Abstract A process is disclosed with integrated steps for fabricating bipolar and CMOS transistors. Mask, patterning and implanting steps are highly integrated to reduce the fabrication complexity. The integrated steps include a split level polysilicon step wherein PMOS and NMOS (168, 170) gate conductors and a bipolar emitter structure (142) is formed. The polysilicon is heavily doped which forms MOS transistor gate electrodes (168, 170), and another high impurity concentration area (188) which is later diffused into an underlying bipolar base region. Small area, high performance transistors can be fabricated with laterally extending contact strips for the collector (216) base (210, 218) and emitter (214) of the bipolar transistor and for the gates (236, 254) source (232, 248) and drain (238, 252) of CMOS transistors. Alignment of electrode metallization patterns is thus less critical.
Inventors
- 👤 Rajiv R. Shah
- 👤 Toan Tran
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 05:45
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
99 words
A method of fabricating a bipolar transistor, comprising the steps of: forming a semiconductor tank on a substrate circumferentially surrounded by a field insulator; forming a base, an emitter and a collector semiconductor region in said semiconductor tank; forming a conductive polycrystalline silicon overlying said emitter region; forming metal strips in contact with each said base region, said polycrystalline and said collector region, said polycrystalline and said collector region, said polycrystalline extending laterally over said field insulator; reacting said metal to form conductive silicide contact strips; and forming a terminal electrode in contact with each said silicide contact strip.
Claim 2
Independent Claim
99 words
A method of fabricating a bipolar transistor, comprising the steps of: forming a semiconductor tank on a substrate circumferentially surrounded by a field insulator; forming a base, an emitter and a collector semiconductor region in said semiconductor tank; forming a conductive polycrystalline silicon overlying said emitter region; forming metal strips in contact with each said base region, said polycrystalline and said collector region, said polycrystalline and said collector region, said polycrystalline extending laterally over said field insulator; reacting said metal to form conductive silicide contact strips; and forming a terminal electrode in contact with each said silicide contact strip.
Claim 3
Dependent Claim
77 words
The method of Claim 1 further including forming said emitter region as a nested structure defined by the formation of a thin insulator on said base region, forming an aperture in said thin insulator, forming said polycrystalline silicon as a heavily doped layer over said aperture so as to be in contact with said base region through said aperture, and patterning said polycrystalline silicon around said aperture so as to overly said thin insulator proximate said aperture.
Claim 4
Dependent Claim
34 words
The method of Claim 2 further including forming a sidewall oxide on said polycrystalline silicon, and forming an extrinsic semiconductor base region in said base region self aligned with respect to said sidewall oxide.
Claim 5
Dependent Claim
30 words
The method of Claim 3 further including forming said emitter region by diffusing the dopant of said polycrystalline silicon into that part of said base region exposed by said aperture.
Claim 6
Dependent Claim
72 words
The method of Claim 1 further including forming said emitter region as a walled structure defined by the formation of a thin insulator formed on said base region, forming an aperture in said insulator, forming said polycrystalline silicon as a heavily doped layer over said aperture and in contact with said base region through said aperture, and patterning said polycrystalline silicon with edges in substantial registry with the edges of said aperture.
Claim 7
Dependent Claim
30 words
The method of Claim 5 further including forming said emitter region by diffusing the dopant of said polycrystalline silicon into that part of said base region exposed by said aperture.
Claim 8
Independent Claim
515 words
A method of fabricating a bipolar transistor, comprising the steps of: forming a first and second semiconductor tank of a first conductivity type, each said tank being laterally insulated by a circumscribing insulating material, and said tanks defining areas for forming a respective bipolar transistor and a MOS transistor of a first type; forming a third semiconductor tank of a second conductivity type, said third tank being insulated from said first and second tanks by an insulating material, and said third tank defining an area for forming therein a MOS transistor of a second type; forming a first thin insulating layer and a first polycrystalline silicon layer over said first, second and third tanks; forming a contiguous intrinsic and extrinsic semiconductor region in said first tank thereby defining an intrinsic and extrinsic base region of the bipolar transistor; patterning said first thin insulating layer and said first polycrystalline silicon layer to form an opening in said first tank to thereby define an emitter region of the bipolar transistor and form an annular island in said second and third tanks to thereby define respective gate elements of the MOS transistors of the first and second type; forming a second polycrystalline silicon layer overlying said first polycrystalline silicon layer for defining areas corresponding to an emitter conductor in said first tank and a gate conductor in each said second and third tank; doping the second polycrystalline silicon layer with an impurity and simultaneously forming a pair of semiconductor regions in said third tank to form MOS transistor source and drain regions; driving the impurity doping in said second polycrystalline silicon layer overlying said first tank into said intrinsic base regions; forming a semiconductor region of a second conductivity type in said extrinsic base region, and forming a pair of semiconductor regions of a second conductivity type in said second tank to thereby form a MOS transistor source and drain region; forming a second thin insulating layer over said second polycrystalline layer and forming a layer of conductive material over said polycrystalline gates associated with said second and third tanks and over the emitter associated with said first tank; forming a strip of said second thin insulating layer and said conductive material over said heavily doped intrinsic base region and over said circumscribing insulating material adjacent thereto; forming a deep collector in said first tank forming a strip of said second thin insulating layer and a conductive material over said deep collector and over the adjacent insulating material; forming a plurality of strips over said second thin insulating layer and said conductive material overlying the drain regions of the respective first and second type MOS transistors, each said strip also overlying a portion of the insulating material adjacent the respective source and drain regions of said MOS transistors; reacting the second thin insulating layer with the conductive material to form a silicide; and forming electrical contacts to said silicide to thereby provide electrical connections to the base, emitter and collector regions of the bipolar transistor, and to the source, drain and gate elements of the respective MOS transistors.
Claim 9
Independent Claim
515 words
A method of fabricating a bipolar transistor, comprising the steps of: forming a first and second semiconductor tank of a first conductivity type, each said tank being laterally insulated by a circumscribing insulating material, and said tanks defining areas for forming a respective bipolar transistor and a MOS transistor of a first type; forming a third semiconductor tank of a second conductivity type, said third tank being insulated from said first and second tanks by an insulating material, and said third tank defining an area for forming therein a MOS transistor of a second type; forming a first thin insulating layer and a first polycrystalline silicon layer over said first, second and third tanks; forming a contiguous intrinsic and extrinsic semiconductor region in said first tank thereby defining an intrinsic and extrinsic base region of the bipolar transistor; patterning said first thin insulating layer and said first polycrystalline silicon layer to form an opening in said first tank to thereby define an emitter region of the bipolar transistor and form an annular island in said second and third tanks to thereby define respective gate elements of the MOS transistors of the first and second type; forming a second polycrystalline silicon layer overlying said first polycrystalline silicon layer for defining areas corresponding to an emitter conductor in said first tank and a gate conductor in each said second and third tank; doping the second polycrystalline silicon layer with an impurity and simultaneously forming a pair of semiconductor regions in said third tank to form MOS transistor source and drain regions; driving the impurity doping in said second polycrystalline silicon layer overlying said first tank into said intrinsic base regions; forming a semiconductor region of a second conductivity type in said extrinsic base region, and forming a pair of semiconductor regions of a second conductivity type in said second tank to thereby form a MOS transistor source and drain region; forming a second thin insulating layer over said second polycrystalline layer and forming a layer of conductive material over said polycrystalline gates associated with said second and third tanks and over the emitter associated with said first tank; forming a strip of said second thin insulating layer and said conductive material over said heavily doped intrinsic base region and over said circumscribing insulating material adjacent thereto; forming a deep collector in said first tank forming a strip of said second thin insulating layer and a conductive material over said deep collector and over the adjacent insulating material; forming a plurality of strips over said second thin insulating layer and said conductive material overlying the drain regions of the respective first and second type MOS transistors, each said strip also overlying a portion of the insulating material adjacent the respective source and drain regions of said MOS transistors; reacting the second thin insulating layer with the conductive material to form a silicide; and forming electrical contacts to said silicide to thereby provide electrical connections to the base, emitter and collector regions of the bipolar transistor, and to the source, drain and gate elements of the respective MOS transistors.
Claim 10
Dependent Claim
30 words
The method of Claim 7 wherein said intrinsic and said extrinsic base regions are formed simultaneously by an implant through both said first thin insulating and said first polycrystalline silicon.
Claim 11
Dependent Claim
30 words
The method of Claim 7 further including forming a metal silicide contact on said deep collector, said silicide contact being formed over the insulating material associated with said first tank.
Claim 12
Dependent Claim
39 words
The method of Claim 7 further including forming a conformal layer of silicon, and anisotropically removing said conformal layer so that a portion of the conformal layer remains on the sidewalls of the polycrystalline emitter and the gate elements.
Claim 13
Independent Claim
238 words
A method of fabricating integrated bipolar and MOS transistors, comprising the steps of: simultaneously forming a pair of semiconductor tanks of a first conductivity type to define a bipolar transistor location and a MOS transistor location of a first type; simultaneously forming a pair of semiconductor tanks of a second conductivity type to define a MOS transistor location of a second type and a region for isolating said semiconductor tanks of said first conductivity type; forming a semiconductor base region in said bipolar transistor location; simultaneously forming a gate insulator and a gate conductor in both said MOS transistor locations and an emitter insulator and an emitter conductor pattern defining an emitter region in said base region of said bipolar transistor location; simultaneously implanting said emitter conductor and the tank of the MOS transistor of said second type to form a source and drain region therein; diffusing the implant impurity from said emitter conductor into said base region to form the emitter region; forming a semiconductor collector region in the tank associated with said bipolar transistor; simultaneously forming a heavily doped semiconductor region in said base region of the bipolar transistor and semiconductor source and drain regions in the tank associated with said MOS transistor of the first type; and simultaneously forming plural terminal conductors contacting said base, emitter and collector regions of said bipolar transistor, and said gate, drain and source regions of the respective MOS transistors.
Claim 14
Independent Claim
238 words
A method of fabricating integrated bipolar and MOS transistors, comprising the steps of: simultaneously forming a pair of semiconductor tanks of a first conductivity type to define a bipolar transistor location and a MOS transistor location of a first type; simultaneously forming a pair of semiconductor tanks of a second conductivity type to define a MOS transistor location of a second type and a region for isolating said semiconductor tanks of said first conductivity type; forming a semiconductor base region in said bipolar transistor location; simultaneously forming a gate insulator and a gate conductor in both said MOS transistor locations and an emitter insulator and an emitter conductor pattern defining an emitter region in said base region of said bipolar transistor location; simultaneously implanting said emitter conductor and the tank of the MOS transistor of said second type to form a source and drain region therein; diffusing the implant impurity from said emitter conductor into said base region to form the emitter region; forming a semiconductor collector region in the tank associated with said bipolar transistor; simultaneously forming a heavily doped semiconductor region in said base region of the bipolar transistor and semiconductor source and drain regions in the tank associated with said MOS transistor of the first type; and simultaneously forming plural terminal conductors contacting said base, emitter and collector regions of said bipolar transistor, and said gate, drain and source regions of the respective MOS transistors.
Claim 15
Dependent Claim
23 words
The method of Claim 11 further including the step of forming a buried contact between said emitter conductor and said semiconductor emitter region.
Claim 16
Dependent Claim
26 words
The method of Claim 12 further including forming said buried contact by forming a conductive polycrystalline silicon between said emitter region and said emitter terminal conductor.
Claim 17
Dependent Claim
58 words
The method of Claim 11 further including simultaneously forming a sidewall insulation on said bipolar transistor emitter conductor and on said MOS transistor conductors for spacing said semiconductor emitter region laterally from other semiconductor regions and for spacing said source and drain semiconductor regions of said respective MOS transistors to form a conduction channel of a desired length.
Claim 18
Dependent Claim
24 words
The method of Claim 14 further including forming said bipolar transistor sidewall insulation to space apart said emitter region from an extrinsic base region.
Claim 19
Independent Claim
179 words
A method of forming contacts to integrated bipolar and field effect transistors, comprising the steps of: forming a base, an emitter and a collector semiconductor region at the face of a semiconductor body to thereby define said bipolar transistor; forming a spaced apart source and drain semiconductor region at the face of the semiconductor body, and a gate structure to form a conduction channel therebetween, to thereby define said field effect transistor; forming said bipolar and said field effect transistor at least partially surrounded by an insulating material; forming a metal conductor layer over said bipolar and field defect transistors over said insulating layer; reacting said metal to form a conductive silicide; patterning said reacted metal to form conductor strips contacting said base, said emitter and said collector semiconductor regions, and to form conductor strips contacting said source and said drain semiconductor regions and said gate structure; patterning at least one said conductor strip of said bipolar transistor and said field effect transistor so as to overlay said insulating material; and forming contact electrodes to each said patterned strip.
Claim 20
Independent Claim
179 words
A method of forming contacts to integrated bipolar and field effect transistors, comprising the steps of: forming a base, an emitter and a collector semiconductor region at the face of a semiconductor body to thereby define said bipolar transistor; forming a spaced apart source and drain semiconductor region at the face of the semiconductor body, and a gate structure to form a conduction channel therebetween, to thereby define said field effect transistor; forming said bipolar and said field effect transistor at least partially surrounded by an insulating material; forming a metal conductor layer over said bipolar and field defect transistors over said insulating layer; reacting said metal to form a conductive silicide; patterning said reacted metal to form conductor strips contacting said base, said emitter and said collector semiconductor regions, and to form conductor strips contacting said source and said drain semiconductor regions and said gate structure; patterning at least one said conductor strip of said bipolar transistor and said field effect transistor so as to overlay said insulating material; and forming contact electrodes to each said patterned strip.
Claim 21
Dependent Claim
37 words
The method of Claim 16 further including forming a buried emitter contact of said bipolar transistor by forming a conductive doped polycrystalline silicon over said emitter semiconductor region, and forming said metal conductor over said polycrystalline silicon.
Claim 22
Dependent Claim
116 words
A vertical bipolar transistor, comprising: a semiconductor substrate; a semiconductor collection region; a semiconductor base region formed in said collector region in a face of said substrate; an insulating layer formed overlying at least a portion of said base region, said insulating layer having an opening defining an underlying emitter area; a semiconductor emitter region in said base region and registered with said opening; a polycrystalline layer overlying said insulating layer and formed through said opening in contact with said emitter region; a first metal conductor silicided to said polycrystalline emitter layer; a second conductor means for making electrical contact with said base region; and third conductor means for making electrical contact with said collector region.
Claim 23
Dependent Claim
116 words
A vertical bipolar transistor, comprising: a semiconductor substrate; a semiconductor collection region; a semiconductor base region formed in said collector region in a face of said substrate; an insulating layer formed overlying at least a portion of said base region, said insulating layer having an opening defining an underlying emitter area; a semiconductor emitter region in said base region and registered with said opening; a polycrystalline layer overlying said insulating layer and formed through said opening in contact with said emitter region; a first metal conductor silicided to said polycrystalline emitter layer; a second conductor means for making electrical contact with said base region; and third conductor means for making electrical contact with said collector region.
Claim 24
Dependent Claim
27 words
The vertical bipolar transistor of Claim 18 wherein said second and third conductor means comprise a conductive metal silicided to the respective semiconductor base and collector regions.
Claim 25
Dependent Claim
34 words
The vertical bipolar transistor of Claim 19 further including a thick insulator for lateral isolation of said transistor, and said second and third conductor means are disposed over a portion of said thick insulator.
Claim 26
Dependent Claim
35 words
The vertical bipolar transistor of Claim 20 further including a passivating layer of insulating material formed over said transistor, said passivating layer including contact openings for providing access to said first, second and third conductors.
Claim 27
Dependent Claim
40 words
The vertical bipolar transistor of Claim 18 further including a heavily doped semiconductor region and a silicide interface between said second conductor mean and said base region and a silicide interface between said third conductor means and said collector region.
Claim 28
Dependent Claim
30 words
The vertical bipolar transistor of Claim 18 wherein said base includes an intrinsic region where bipolar transistor action occurs, and an extrinsic region for contact with said second conductor means.
Claim 29
Dependent Claim
20 words
The vertical bipolar transistor of Claim 19 further including a second silicided contact formed in contact with said base region.
Claim 30
Dependent Claim
76 words
A small area bipolar transistor, comprising: a semiconductor tank formed in a face of a semiconductor body, said tank forming a collector region of said transistor; a semiconductor moat formed in said tank, said moat forming an active intrinsic base region of said transistor; an emitter region formed in said base region; an extrinsic base region formed in said moat; and means for electrically contacting said extrinsic base region, said emitter region and said collector region.
Claim 31
Dependent Claim
76 words
A small area bipolar transistor, comprising: a semiconductor tank formed in a face of a semiconductor body, said tank forming a collector region of said transistor; a semiconductor moat formed in said tank, said moat forming an active intrinsic base region of said transistor; an emitter region formed in said base region; an extrinsic base region formed in said moat; and means for electrically contacting said extrinsic base region, said emitter region and said collector region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.