Method and arrangement for addressing redundant elements in an integrated memory

Abstract

Abstract The invention relates to a method of addressing redundant elements of an integrated memory (M) which comprises a network of row memory elements and column memory elements which can be addressed respectively via row addresses and column addresses, at least one bank (B) of fuses for storing the address of a defective element of the memory; the method consisting in:… - for a bank (B), associating this bank with a row and column address pair;… - storing, by blowing certain fuses in the bank, after testing a memory element, the address of either a column element in the case where the defective element is a column element, or a row element in the case where the defective element is a row element;… - and checking only the row addresses when the stored address is that of a r ow element or only the column addresses when the stored address is that of a column element in order to address either a redundant row element, or a redundant column element. …<IMAGE>…

Inventors

• 👤 Jean-Marie Bernard Gaultier
• 👤 Jean Devin

Bibliographic Details