Patent EP0293578A2 successfully refreshed from Google Patents.
EP0293578A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
High density layout for memory arrays
Assignee: International Business Machines Corp
•
Filing: 1988-04-12
•
Granted: —
•
Expires: 2008-04-12
Abstract
Abstract This invention relates to the layout of memory cells (1) and their associated pair of bit lines in such a way that very high density arrays are obtainable. The resulting memory cell array is one in which the bit lines (B02, B03) associated with each column of memory cells are interleaved with the bit lines of (B11, B12) adjacent columns of memory cells. By this means, regions of the semiconductor chip in which the cells are formed, which were formerly unusable, now become usable and cell area is significantly reduced. Because the spacing of metallic bit lines is governed by certain ground rules, cell length in the x-dimension could be reduced no further as long as metallic interconnections were used. To overcome this limitation, polycrystalline fingers or extensions (13) are substituted for metal cross-coupling interconnections. Because polycrystalline interconnections have less stringent requirements relative to their spacing, using such interconnections in conjunction with metallic straps (14) which are shorter than the widths and spacing of two metallic interconnection lines again provides a significant reduction in the x-dimension and hence in cell area. When interleaved bit lines, polycrystalline fingers (13) and straps (14) are used at the same time instead of metal interconnections, both approaches provide a memory cell area which is significantly improved over cell areas when neither or only one of the approaches taught are used. The method and structure taught may be utilized with both bipolar and unipolar devices.
Inventors
- 👤 Kurt Ganssloser
- 👤 Dieter F. Wendel
- 👤 Siegfried K. Wiedmann
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 01:22
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; H; H10; H10B; H10B10/00; H10B10/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
70 words
A memory array comprising a plurality of memory cells (1) arranged in rows and columns, each said row of said memory cells having an associated word line; and each said column of memory cells having an associated pair of bit lines at least one (B02, B03) of said pair of bit lines of each column being interleaved with the bit line (B11, B12) of an adjacent column of memory cells.
Claim 2
Dependent Claim
70 words
A memory array comprising a plurality of memory cells (1) arranged in rows and columns, each said row of said memory cells having an associated word line; and each said column of memory cells having an associated pair of bit lines at least one (B02, B03) of said pair of bit lines of each column being interleaved with the bit line (B11, B12) of an adjacent column of memory cells.
Claim 3
Dependent Claim
32 words
A memory array according to claim 1 wherein each of said memory cells includes a pair of cross-coupled devices one terminal of each of said pair being connected to a word line.
Claim 4
Dependent Claim
52 words
A memory array according to claim 1 or 2 wherein each of said memory cells includes a pair of input devices one of which is connected to one of said associated pair of bit lines and the other of which is connected to the other of said associated pair of bit lines.
Claim 5
Dependent Claim
62 words
A memory array according to claims 1 to 3 wherein each of said memory cells includes first npn and pnp transistors spaced from second npn and pnp transistors by an isolation region (10) and further including means (9; 13, 14) extending across said isolation region (10) for cross-coupling a pair of n and p regions of said first and second npn transistors.
Claim 6
Dependent Claim
123 words
A memory array according to claim 4 wherein said means for cross-coupling a pair of n and p regions includes a first polycrystalline element (11) connected to a p-region of said first npn transistor said first element having a finger-like extension (13) extending across said isolation region (10) and terminating in the vicinity of an n-region of said second npn transistor and a second polycrystalline element (11) connected to a p-region of said second npn transistor said second element having a finger-like extension (13) extending across said isolation region (10) and terminating in the vicinity of an n-region of said first npn transistor, said extensions (13) of said first and second polycrystalline elements (11) being connected to said n-regions by metallic interconnections (14).
Claim 7
Dependent Claim
123 words
A memory array according to claim 4 wherein said means for cross-coupling a pair of n and p regions includes a first polycrystalline element (11) connected to an n-region of said first pnp transistor said first element (11) having a finger-like extension (13) extending across said isolation region (10) and terminating in the vicinity of a p-region of said second pnp transistor and a second polycrystalline element (11) connected to an n-region of said second pnp transistor said second element having a finger-like extension (13) extending across said isolation region and terminating in the vicinity of a p-region of said first pnp transistor, said extensions (13) of said first and second polycrystalline elements (11) being connected to said p-regions by metallic interconnections (14).
Claim 8
Dependent Claim
181 words
A memory array comprising a plurality of memory cells (1) arranged in rows and columns each said row of said memory cells having an associated word line, each of said memory cells including first and second pairs of complementary transistors spaced from each other by an isolation region (10), a first polycrystalline element (11) connected to a region of first conductivity type of one of said first pair of complementary transistors, said first element having a finger-like extension (13) extending across said isolation region (10) and terminating in the vicinity of a region of second conductivity type of one of said second pair of complementary transistors, and a second polycrystalline element (11) connected to a region of first conductivity type of said one of said second pair of complementary transistors, said second element having a finger-like extension (13) extending across said isolation region (10) and terminating in the vicinity of a region of second conductivity type of said one of said first pair of complementary transistors, said extensions being connected to said regions of second conductivity type by metallic interconnections (14).
Claim 9
Dependent Claim
181 words
A memory array comprising a plurality of memory cells (1) arranged in rows and columns each said row of said memory cells having an associated word line, each of said memory cells including first and second pairs of complementary transistors spaced from each other by an isolation region (10), a first polycrystalline element (11) connected to a region of first conductivity type of one of said first pair of complementary transistors, said first element having a finger-like extension (13) extending across said isolation region (10) and terminating in the vicinity of a region of second conductivity type of one of said second pair of complementary transistors, and a second polycrystalline element (11) connected to a region of first conductivity type of said one of said second pair of complementary transistors, said second element having a finger-like extension (13) extending across said isolation region (10) and terminating in the vicinity of a region of second conductivity type of said one of said first pair of complementary transistors, said extensions being connected to said regions of second conductivity type by metallic interconnections (14).
Claim 10
Dependent Claim
55 words
A memory array according to claim 7 further including a plurality of pairs of bit lines each pair of bit lines being connected to an associated column of memory cells, at least one of said pair of bit lines of each column being interleaved with the bit line of an adjacent column of memory cells.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.