Patent EP0304236A2 successfully refreshed from Google Patents.
EP0304236A2
Expired / Lapsed
EP
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Video signal processing apparatus
Assignee: Sony Corp
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Filing: 1988-08-11
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Granted: —
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Expires: 2008-08-11
Abstract
Abstract In a memory control apparatus for providing various video display functions by means of a video memory (13) into which video data (DATA IN ) constituting successive units, such as frames or fields, of video information are written at repeatedly changing write addresses while concurrently reading out the data (DATA OUT ) from repeatedly changing read-out addresses, the video memory (13) is provided with at least four memory areas (M11, M21, M31; M12, M22, M32; M13, M23, M33; M14, M24, M34) each having a capacity to store one of the units of video information. Impending overtaking of the write and read-out addresses relative to each other is detected by write or read-out address overtake detecting circuits (42, 43) and, in response to such detection, the one of the memory areas in which the data is being written or read-out is changed by a frame assignment switching circuit (33) or by a frame selection switching circuit (34) so as to maintain a separation of the write and read-out addresses sufficient to ensure avoidance of overtaking and consequent disturbance of the displayed image.
Inventors
- 👤 Yutaka C/O Patents Division Sonoda
- 👤 Hirofumi C/O Patents Division Yuchi
- 👤 Kyoichi C/O Patents Division Murakami
- 👤 Masaharu C/O Patents Division Tokuhara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 12:52
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/445; G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/399; H04N5/45; H04N5/76; H04N5/907
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
452 words
Video signal processing apparatus comprising: a first input terminal (T2) supplied with a first analog video signal (VIDEO2) including successive units of video information and first synchronising signals; a second input terminal (T1) supplied with a second analog video signal (VIDEO1) including second synchronising signals; analog-to-digital converter means (12) connected to said first input terminal (T2) for converting said first analog video signal (VIDEO2) to corresponding digital data (DATA IN ); memory means (31) having at least four successively numbered unit areas (e.g. M11, M12, M13, M14) each being capable of storing said digital data corresponding to one of said units of said first analog video signal; writing unit area selecting means (33) for selecting one of said four unit areas as a writing unit of said memory means (31) in which digital data corresponding to a unit of said first analog video signal is to be stored; reading unit area selecting means (34) for selecting one of said four unit areas as a reading unit area of said memory means (31) from which digital data corresponding to a unit of said first analog video signal is to be read out; digital-to-analog converter means (23) connected to said reading area selecting means (34) for converting the read-out digital data to a read-out analog video signal (S OUT2 ); writing clock signal generator means (14) for generating writing clock signals (WCK) synchronised with said first synchronising signals; writing address control means (15) for generating writing address signals (WADR) and writing unit signals (PFW), and being supplied with said writing clock signals (WCK); writing unit area control means (41) supplied with said writing unit signals (PFW) for generating a writing unit area control signal (S12) to control said writing area selecting means (33); reading clock signal generator means (21) for generating reading clock signals (RCK) synchronised with said second synchronising signals; reading address control means (22) for generating reading address signals (RADR) and reading unit signals (PFR), and being supplied with said reading clock signals (RCK); reading unit area control means (44) supplied with said reading unit signals (PFR) for generating a reading unit area control signal (S14) to control said reading unit area selecting means (34); and detecting means (42, 43) supplied with said writing unit area control signal (S12) and said reading unit area control signal (S14) for detecting the number of said writing unit area and the number of said reading unit area which are adjacent to each other and for controlling one of said writing unit area control means (41) and said reading unit area control means (44) so as to distance said number of said writing unit area and said number of said reading unit area from each other.
Claim 2
Dependent Claim
452 words
Video signal processing apparatus comprising: a first input terminal (T2) supplied with a first analog video signal (VIDEO2) including successive units of video information and first synchronising signals; a second input terminal (T1) supplied with a second analog video signal (VIDEO1) including second synchronising signals; analog-to-digital converter means (12) connected to said first input terminal (T2) for converting said first analog video signal (VIDEO2) to corresponding digital data (DATA IN ); memory means (31) having at least four successively numbered unit areas (e.g. M11, M12, M13, M14) each being capable of storing said digital data corresponding to one of said units of said first analog video signal; writing unit area selecting means (33) for selecting one of said four unit areas as a writing unit of said memory means (31) in which digital data corresponding to a unit of said first analog video signal is to be stored; reading unit area selecting means (34) for selecting one of said four unit areas as a reading unit area of said memory means (31) from which digital data corresponding to a unit of said first analog video signal is to be read out; digital-to-analog converter means (23) connected to said reading area selecting means (34) for converting the read-out digital data to a read-out analog video signal (S OUT2 ); writing clock signal generator means (14) for generating writing clock signals (WCK) synchronised with said first synchronising signals; writing address control means (15) for generating writing address signals (WADR) and writing unit signals (PFW), and being supplied with said writing clock signals (WCK); writing unit area control means (41) supplied with said writing unit signals (PFW) for generating a writing unit area control signal (S12) to control said writing area selecting means (33); reading clock signal generator means (21) for generating reading clock signals (RCK) synchronised with said second synchronising signals; reading address control means (22) for generating reading address signals (RADR) and reading unit signals (PFR), and being supplied with said reading clock signals (RCK); reading unit area control means (44) supplied with said reading unit signals (PFR) for generating a reading unit area control signal (S14) to control said reading unit area selecting means (34); and detecting means (42, 43) supplied with said writing unit area control signal (S12) and said reading unit area control signal (S14) for detecting the number of said writing unit area and the number of said reading unit area which are adjacent to each other and for controlling one of said writing unit area control means (41) and said reading unit area control means (44) so as to distance said number of said writing unit area and said number of said reading unit area from each other.
Claim 3
Dependent Claim
43 words
Apparatus according to claim 1, comprising display means (26) and switch means (24) for selectively supplying one of said read-out analog video signals (S OUT2 ) from said digital-to-analog converter means (23) and said second analog video signal to said display means (26).
Claim 4
Dependent Claim
144 words
Apparatus according to claim 1 or claim 2, wherein said memory means (31) is divided into three memory areas (MEM1, MEM2, MEM3) each including one third of each of said four unit areas, and said apparatus comprises: writing memory area selecting means (32) connected between said analog-to-digital converter means (12) and said writing unit area selecting means (33) for selecting one of said three memory areas (MEM1, MEM2, MEM3); reading memory area selecting means (36) connected between said reading unit area selecting means (34) and said digital-to-analog converter means (23) for selecting one of said three memory areas (MEM1, MEM2, MEM3); means (51) for controlling said writing memory area selecting means (32) and being synchronised with said writing address control means (15); and means (52) for controlling said reading memory area selecting means (36) and being synchronised with said reading address control means (22).
Claim 5
Dependent Claim
33 words
Apparatus according to claim 3, wherein said digital data is written in one of said three memory areas concurrently with the transfer of digital data from the others of said three memory areas.
Claim 6
Dependent Claim
79 words
Apparatus according to claim 4, comprising parallel-to-serial converting means (35) connected between said reading unit area selecting means (34) and said reading memory area selecting means (36), and wherein said means (51) for controlling the writing memory area selecting means is operable to transfer the digital data stored in said memory means (31) to said parallel-to-serial converting means (35) in response to a demand for such transfer from said means (52) for controlling the reading memory area selecting means.
Claim 7
Dependent Claim
106 words
Apparatus according to any one of the preceding claims, wherein said detecting means (42,43) includes means for determining when said writing unit area is one unit behind said reading unit area and, in response thereto, controlling said writing unit area control means (41) so as to twice write a unit of said digital data in the same writing unit area, and means for determining when said reading unit area is one unit behind said writing unit area and, in response thereto, controlling said reading unit area control means (44) so as to twice read a unit of said digital data from the same reading unit area.
Claim 8
Dependent Claim
27 words
Apparatus according to any one of the preceding claims, wherein said reading address signals (RADR) are operable to designate every other address of said memory means (31).
Claim 9
Dependent Claim
27 words
Apparatus according to any one of the preceding claims, wherein said writing address signals (WADR) are operable to designate every other address of said memory means (31).
Claim 10
Dependent Claim
19 words
Apparatus according to any one of claims 1 to 8, wherein said successive units of video information are frames.
Claim 11
Dependent Claim
19 words
Apparatus according to any one of claims 1 to 8, wherein said successive units of video information are fields.
Claim 12
Dependent Claim
119 words
Apparatus according to claim 10, wherein said detecting means (42,43) includes means for detecting when the writing field area is one field behind the reading field area and, in response thereto, controlling the writing field area control means (41) so as to write a field of said digital data in one of the field areas which is two fields behind the detected writing field area, and means for detecting when the reading field area is one field behind the writing field area and, in response thereto, controlling the reading field control means (44) so as to read a field of said digital data from one of the field areas which is two fields behind the detected reading field area.
Claim 13
Dependent Claim
110 words
Apparatus according to claim 10, wherein said detecting means (42,43) includes means for detecting when the writing field area is one field behind the reading field area and, in response thereto, controlling the writing field area control means (41) so as to write a field of said digital data in one of the field areas which is one field behind the detected writing field area, and means for detecting when the reading field area is one field behind the writing field area and, in response thereto, controlling the reading field control means (44) so as to twice read a field of said digital data from the same reading field area.
Claim 14
Dependent Claim
69 words
Apparatus according to claim 12, wherein said first analog video signal (VIDEO2) has alternating odd and even fields (O,E) providing respective images which are to be interlaced for display, the apparatus comprising means (27) responsive to said detecting means (42,43) to cause said reading address control means (22) to shift said reading address signals (RADR) by one line for every other one of said odd and even fields (O,E).
Claim 15
Dependent Claim
145 words
Video signal processing apparatus comprising: memory means (31) responsive to a writing address signal (WADR) to write in data corresponding to an input video signal (DATA IN ), and responsive to a reading address signal (RADR) to read out the data written therein thereby to provide an output video signal for display, wherein the memory means (31) comprises at least four unit areas (e.g. M11, M12, M13, M14) for sequential accessing in a predetermined order; and detecting means (42, 43) for detecting when the number of a writing unit area designated by the writing address signal (WADR) and the number of a reading unit area designated by the reading address signal (RADR) are adjacent to each other and, in response to the detection, controlling the writing or reading address signal (WADR, RADR) so as to distance the numbers of the writing and reading unit areas.
Claim 16
Dependent Claim
145 words
Video signal processing apparatus comprising: memory means (31) responsive to a writing address signal (WADR) to write in data corresponding to an input video signal (DATA IN ), and responsive to a reading address signal (RADR) to read out the data written therein thereby to provide an output video signal for display, wherein the memory means (31) comprises at least four unit areas (e.g. M11, M12, M13, M14) for sequential accessing in a predetermined order; and detecting means (42, 43) for detecting when the number of a writing unit area designated by the writing address signal (WADR) and the number of a reading unit area designated by the reading address signal (RADR) are adjacent to each other and, in response to the detection, controlling the writing or reading address signal (WADR, RADR) so as to distance the numbers of the writing and reading unit areas.
References Cited (Backward Citations)
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