Dual rail processors with error checking on i/o reads

Claim 2

A dual processor data processing system with interprocessor error checking comprising: a first central processing unit executing a series of in­structions; a second central processing unit executing said series of instructions independently of and in synchronism with said first central processing unit; a first data bus coupled to said first central processing unit for receiving data to be input to said first central pro­cessing unit; a second data bus coupled to said second central processing unit for receiving data to be input to said second central pro­cessing unit; error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses and for detecting errors on I/O reads prior to delivery of said data to said first and second central processing units, said error checking means including comparison means for indicating an error when said data on said first and second data busses are unequal; and error isolation means, responsive to an error detected from said error checking means, for analyzing the cause of error while maintaining system synchronization.

Claim 3

The dual processor data processing system of claim 1 further including a main memory unit coupled to both said first and second central processing units, and wherein said error checking means includes memory controller means for indicating the presence of an error when said input data on said first and second input busses are unequal.

Claim 4

The dual processor data processing system of claim 2 wherein said memory controller means includes a primary memory controller coupled to said first data bus and including means for transferring data from said first data bus to said main memory unit, and a mirror memory controller coupled to said second bus and including means for comparing the data from said second data bus with the data from said first data bus for purposes of error checking.

Claim 5

A fault tolerant computing system comprising: a first processing system including a first central processing unit executing a series of instructions, a second central processing unit executing said series of instructions independently of and in synchronism with said first central processing unit, a first data bus coupled to said first central pro­cessing unit for receiving data to be input to said first central processing unit, a second data bus coupled to said second central pro­cessing unit for receiving data to be input to said second central processing unit, and first error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses and for detecting errors on I/O reads prior to delivery of said data to said first and sec­ond central processing units, said first error checking means including first comparison means for indicating an error when said data on said first and second data busses are unequal; a second processing system operating substantially synchro­nously with said first processing system, said second processing system including a third central processing unit executing said series of instructions, a fourth central processing unit executing said series of instructions independently of and in synchronism with said third central processing unit, a third data bus coupled to said third central pro­cessing unit for receiving data to be input to said third central processing unit, a fourth data bus coupled to said fourth central pro­cessing unit for receiving data to be input to said fourth central processing unit, and second error checking means, coupled to said third and fourth data busses and for checking data transmitted over said third and fourth data busses for detecting errors on I/O reads prior to delivery of said data to said third and fourth processing systems, said second error checking means including second comparison means for indicating an error when said data on said third and fourth data busses are un­equal; and cross-link communication means coupled between said first and second processing systems for providing bidirectional syn­chronous communication between said first and second processing systems.

Claim 6

A fault tolerant computing system comprising: a first processing system including a first central processing unit executing a series of instructions, a second central processing unit executing said series of instructions independently of and in synchronism with said first central processing unit, a first data bus coupled to said first central pro­cessing unit for receiving data to be input to said first central processing unit, a second data bus coupled to said second central pro­cessing unit for receiving data to be input to said second central processing unit, and first error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses and for detecting errors on I/O reads prior to delivery of said data to said first and sec­ond central processing units, said first error checking means including first comparison means for indicating an error when said data on said first and second data busses are unequal; a second processing system operating substantially synchro­nously with said first processing system, said second processing system including a third central processing unit executing said series of instructions, a fourth central processing unit executing said series of instructions independently of and in synchronism with said third central processing unit, a third data bus coupled to said third central pro­cessing unit for receiving data to be input to said third central processing unit, a fourth data bus coupled to said fourth central pro­cessing unit for receiving data to be input to said fourth central processing unit, and second error checking means, coupled to said third and fourth data busses and for checking data transmitted over said third and fourth data busses for detecting errors on I/O reads prior to delivery of said data to said third and fourth processing systems, said second error checking means including second comparison means for indicating an error when said data on said third and fourth data busses are un­equal; and cross-link communication means coupled between said first and second processing systems for providing bidirectional syn­chronous communication between said first and second processing systems.

Claim 7

The dual processor computer system of claim 4 further including: error isolation means, responsive to an error detected from either said first or second error checking means, for analyzing the cause of the error while maintaining said first and second processing system in synchronization.