Apparatus for communication pixel data from RAM memories to a display

Claim 2

Apparatus for serializing 2 M parallel outputs of an all points addressable memory into successive data groups, each data group corresponding to a re­spective value for a pixel in an image wherein the bit-length of the pixel value is selectable, the apparatus characterized by: gate means, having (i) 2 M parallel input junctions connected to the outputs of the memory and (ii) 2 N output junctions, for selectively converting each set of parallel inputs at said input junctions into 2 M-n successive data groups, each data group having a bit-length of 2 n data bits, wherein each data group exits the gate means through 2 n of the 2 n output junctions; and means for communicating to said gate means a signal input which controls the bit-length 2 n of data groups, wherein n is a selectable integer 1 ≦ n ≦ N ≦ M.

Claim 3

The apparatus of Claim 1 wherein the gate means are characterized by: shift register means for receiving as input from the memory successive sets of 2 M parallel bits and for shifting out, for each received input set, 2 M-N successive strings of 2 N ; and multiplexers cascaded over successive levels, wherein each multiplexer in a first level receives as input selected bits of each shifted out string, and wherein each multiplexer in a subsequent level has as input outputs produced by prescribed multi­plexers in the preceding level.

Claim 4

The apparatus of Claim 2 wherein the cascaded multiplexers include 2 N-1 multiplexers in the lth level, where 1 ≦ 1.

Claim 5

The apparatus of Claim 2 wherein the shift re­gister means includes 2 N shift registers, each having a respective output SR(0) through SR(2 N -1); and wherein the gate means are further characterized by a plurality of bit-gate levels wherein each lth level includes 2 N-1 2-to-1 latching multiplexers and 2 N - 2 N-1 latches; wherein each 2-to-1 multiplexer at a first level l = 1 selectively puts out the bit value corresponding to either output SR(i) or SR(i+2 N-1 ) for a respective value of i where i is a value 0 ≦ i ≦ (2 N - 1); wherein each 2-to-1 multiplexer at a level l ≦ 1 selectively puts out the bit value corresponding to either M(j) or for each j where and where M(k) corresponds to the output of the kth multiplexer in the preceding level; and wherein in the first level the output of each shift register SR (2 N/2 )) through SR (2 N -1) enters a respective latch to provide an output in synchrony with the outputs from the first level multiplexers; wherein the output of each latch at a level (L-1) is delayed by a respective latch at level L (where L ≦ total number of levels) and wherein each multiplexer output of a level (L-1) is delayed by a respective latch at a subsequent level L; the final level having only a single 2-to-1 multi­plexer and (2 N - 1) latches, the outputs from the final level multiplexer and final level latches being in synchrony.

Claim 6

The apparatus of Claim 1 wherein the gate means are characterized by: a plurality of 2 M-X parallel 2 X -to-1 multiplexers positioned in a prescribed order, each having a set of 2 X unique VD outputs as respective inputs thereto; means for selecting the qth input to each 2 X -to-1 multiplexer as the output therefrom, where q is an integer 1 ≦ q ≦ 2 X ; a plurality of 2-to-1 multiplexers, each receiving as the first input thereto the output from a respective 2 X -to-1 multiplexer; and means for clocking data through the 2-to-1 multi­plexers as parallel data bits in response to a clock pulse, the data bit from each 2-to-1 multi­plexer being conveyed to a respective output junction SB(i) wherein the data bit at output junction SB(i) represents the second input to the 2-to-1 multiplexer associated with the lower-­ordered output junction SB(i-1) where i is an integer greater than 0; wherein said signal input communicating means includes: means for selecting either the first input or the second input for all of the 2-to-1 multiplexers; and means for selecting predetermined output junctions as video outputs wherein the selection of output junctions depends on the number of bits to be allocated to each pixel.

Claim 7

The apparatus of Claim 5 wherein, in response to a clock pulse by said clocking means when the first inputs to said 2-to-1 multiplexers have been selected, data bits from the 2 X -to-1 multiplexers are conveyed onto output junctions SB(0) through SB (2 X -1); and wherein, in response to a clock pulse by said clocking means when the second inputs to said 2-to-1 multiplexers have been selected, the data bit at each output junction SB(i) is conveyed to a successively lower ordered output junction SB(i-1); wherein said clocking means includes means for clocking bits to successively lower ordered output junctions for no more than 2 M-n clock pulses.

Claim 8

The apparatus of Claim 6 wherein, for 2 n bits/pixel, 2 n output junctions are selected to receive data bits from 2 M-n unique output junctions in sequence in response to successive clock pulses from said clocking means; and wherein the inputs to the 2 X -to-1 multiplexers correspond to the VD outputs rearranged so that, for each of a plurality of 2 n values, the data bits at the video output lines at each clock pulse correspond to a 2 n -bit pixel value formed of consecutive VD output bits.

Claim 9

The apparatus of Claim 7 wherein the gating means are further characterized by 2 n video output lines extending from respective selected output junctions, wherein successive data groups are conveyed along the 2 n video output lines in response to successive clock pulses from said clocking means; and wherein the 2 X -to-1 multiplexers comprise successive sets of multiplexers each multiplexer set having 2 M-n 2 X -to-1 multiplexers; and wherein successive 2 k th inputs for successive multiplexers in a set correspond to VD outputs spaced every 2 k VD outputs.

Claim 10

Apparatus as set forth in one of claims 1 to 8 for displaying image data characterized by: a video display (154); means for serializing parallel outputs VD(0) through VD (2 M ) (where M is an integer) of an all points addressable memory (150) into successive data groups, each data group corresponding to a respective value for a pixel in an image wherein the bit-length of the pixel value is selectable, the serializing means comprising: gate means (152), having (i) 2 M parallel input junctions connected to the outputs of the memory and (ii) 2 N output junctions, for selectively converting each set of 2 M parallel inputs at said input junctions into 2 M-n successive data groups, each data group having a bit-length of 2 n wherein each data group exits the gate means through 2 n of the 2 N output junctions; and means for communicating to said gate means a signal which controls the bit-length 2 n of data groups, wherein n is a selectable integer 1 ≦ n ≦ N ≦ M; and control means for generating a pixel value signal for each data group exitting the gate means and entering the pixel value signals to the display in sequence.

Claim 11

The apparatus of Claim 9 wherein the control means are characterized by: palette memory means (700) for associating each input address thereto with a color indicative value; address means (300) for converting data group inputs into address inputs to said palette memory means; and masking means (600) for selectively entering, as address means input, only data group data on the 2 n of the 2 N output junctions.