Serial video processor and fault-tolerant serial video processor device

Claim 2

A serial video processor system for real-time processing of raster-scanned video, comprising: an input for receiving digitized, multi-bit video data: a plurality of serial video processors, each video processor having: an input register connected to receive said muolti-bit video data from said input; an output register connected to transfer multi-bit processed data from the video processor; first and second reandom-access memories each having data inputs and outputs connected to said input and output registers and each having an address input; a serial ALU having a plurality of one-bit registers and multiplexer means to connect inputs and outputs of each said registers to data inputs and outputs of said first and second random-access memories, the multiplexer means also connecting inputs and outputs of some of the. registers to the serial ALU of adjacent video processors; control inputs in common with all of said video processors receiving control and address sets of bits to select operation of the multiplexer means and addressing of said first and second random-access memories to thereby perform one-bit serial arithmetic/logic operations in each of the video processors for each set of control and address bits; commutator means addressing the input registers of said plurality of serial video processors in, a repeating sequence correlated with a raster scan to load said multi-bit video data from said input into said input registers; said commutator means also addressing the output registers of said plurality of serial video processors in a repeating sequence correlated with a raster scan to transfer processed multi-bit video data to an output; control means having a multi-bit parallel output connected in common to said control inputs of all of said serial video processors to apply sequences of sets of control and address bits to said control inputs to result in real-time processing of said multi-but video data.

Claim 3

A system according to claim 1 wherein an analog system input is connected to said input through an analog-to-digital converter, and said output is connected to an analog system output through a digital-to-analog converter.

Claim 4

A system according to claim 2 wherein said analog system input is sampled at a rate which is related to a multiple of the horizontal scan rate of said raster scan, said multiple being at least equal to the number of serial video processors.

Claim 5

A system according to claim 3 wherein there are at least as many of said serial video processors as there are pixels in a horizontal scan of said raster scan.

Claim 6

A system according to claim 1 wherein said first and second memories comprise a dynamic random access memory having one differential sense amplifier for each of the serial video processors.

Claim 7

A system according to claim 1 wherein said input register of each video processor includes a first set of bits connected to receive said multi-bit video data from said input and a second set of bits connected to outputs of a frame memory.

Claim 8

A system according to claim 6 wherein said output register of each video processor includes a first set of bits connected to transfer said multi-bit processed data from said video processor to said output and a second set of bits connected to transfer processed data to inputs of said frame memory.

Claim 9

A system according to claim 7 wherein there are at least as many of said serial video processors as the number of pixels in a horizontal scan of said raster scan, and there is a delay of at least one of said horizontal scans between input of video data to said input and output of processed data at said output.

Claim 10

A system according to claim 8 wherein said frame memory stores processed video data for one frame of said raster scan.

Claim 11

A serial processor system for high-speed processing comprising: an input for receiving digitized, multi-bit signal data; a plurality of serial processors in a linear array, each serial processor having: an input register connected to receive said multi-bit signal data from said input; an output register connected to transfer multi-bit processed data from the serial processor; random-access memory means having data inputs and outputs connected to said input and output registers and having at least one address input; a serial ALU element having a plurality of one-bit registers and multiplexer means to connect inputs and outputs of each said registers to data inputs and outputs of said random-access memory means, the multiplexer means also capable of connecting inputs and outputs of some of the one-bit registers to the serial ALU element of adjacent serial processors; control inputs in common with all of said serial processors receiving sets of control and address bits to select operation of the multiplexer means and addressing of said random-access memory means to thereby perform one-bit serial arithmetic/logic operations in each of the serial processors for each set of control and address bits; first commutator means addressing the input registers of said plurality of serial processors in a repeating sequence correlated with said signal data to load said multi-bit signal data from said input into said input registers; and second commutator means addressing the output registers of said plurality of serial processors in a repeating sequence to transfer processed multi-bit data to an output; control means having a multi-bit parallel output connected in common to said control inputs and address inputs for all of said serial processors to apply sequences of sets of control and address bits to said control inputs to result in high-speed processing of said multi-bit signal data.

Claim 12

A serial processor system for high-speed processing comprising: an input for receiving digitized, multi-bit signal data; a plurality of serial processors in a linear array, each serial processor having: an input register connected to receive said multi-bit signal data from said input; an output register connected to transfer multi-bit processed data from the serial processor; random-access memory means having data inputs and outputs connected to said input and output registers and having at least one address input; a serial ALU element having a plurality of one-bit registers and multiplexer means to connect inputs and outputs of each said registers to data inputs and outputs of said random-access memory means, the multiplexer means also capable of connecting inputs and outputs of some of the one-bit registers to the serial ALU element of adjacent serial processors; control inputs in common with all of said serial processors receiving sets of control and address bits to select operation of the multiplexer means and addressing of said random-access memory means to thereby perform one-bit serial arithmetic/logic operations in each of the serial processors for each set of control and address bits; first commutator means addressing the input registers of said plurality of serial processors in a repeating sequence correlated with said signal data to load said multi-bit signal data from said input into said input registers; and second commutator means addressing the output registers of said plurality of serial processors in a repeating sequence to transfer processed multi-bit data to an output; control means having a multi-bit parallel output connected in common to said control inputs and address inputs for all of said serial processors to apply sequences of sets of control and address bits to said control inputs to result in high-speed processing of said multi-bit signal data.

Claim 13

A fault-tolerant, serial video device system for real-time processing of raster-scanned video, comprising: an input for receiving digitized, multi-bit video data; a set of N serial video processors, each one of said set of N video processors having: an input register connected to receive said multi-bit video data from said input; an output register connected to transfer multi-bit processed data from the video processor; first and second random-access memories each having data inputs and outputs connected to said input and output registers and each having an address input; a serial ALU having a plurality of one-bit registers and means to connect inputs and outputs of each said registers to data inputs and outputs of said first and second random-access memories, cross-connect means connecting inputs and outpus of the serial ALU to the serial ALU of adjacent video processors on the left and right; control inputs in common with all of said video processors receiving control and address sets of bits to select operation of the sense ALU and addressing of said first and second random-access memories to thereby perform one-bit serial arithmetic/logic operations in each of the set of N video processors for each set of control and address bits; commutator means having N stages addressing the input registers of said set of N serial video processors in a repeating sequence correlated with a raster scan to load said multi-bit video data from said input into said input registers; and commutator means having N stages also addressing the output registers of said set of N serial video processors in a repeating sequence correlated with a raster scan to transfer processed multi-bit video data to an output; control means having a multi-bit parallel output connected in common to said control inputs of all of said serial video processors to apply sequences of sets of control and address bits to said control inputs to result in real-time processing of said multi-bit video data, wherein each of said set of N serial video processors and said commutator include means by-pass means whereby selected ones of said serial video processors are omitted from operation of the device, the number N exceeding the number of processors needed for one line of said scan.

Claim 14

A fault-tolerant, serial video device system for real-time processing of raster-scanned video, comprising: an input for receiving digitized, multi-bit video data; a set of N serial video processors, each one of said set of N video processors having: an input register connected to receive said multi-bit video data from said input; an output register connected to transfer multi-bit processed data from the video processor; first and second random-access memories each having data inputs and outputs connected to said input and output registers and each having an address input; a serial ALU having a plurality of one-bit registers and means to connect inputs and outputs of each said registers to data inputs and outputs of said first and second random-access memories, cross-connect means connecting inputs and outpus of the serial ALU to the serial ALU of adjacent video processors on the left and right; control inputs in common with all of said video processors receiving control and address sets of bits to select operation of the sense ALU and addressing of said first and second random-access memories to thereby perform one-bit serial arithmetic/logic operations in each of the set of N video processors for each set of control and address bits; commutator means having N stages addressing the input registers of said set of N serial video processors in a repeating sequence correlated with a raster scan to load said multi-bit video data from said input into said input registers; and commutator means having N stages also addressing the output registers of said set of N serial video processors in a repeating sequence correlated with a raster scan to transfer processed multi-bit video data to an output; control means having a multi-bit parallel output connected in common to said control inputs of all of said serial video processors to apply sequences of sets of control and address bits to said control inputs to result in real-time processing of said multi-bit video data, wherein each of said set of N serial video processors and said commutator include means by-pass means whereby selected ones of said serial video processors are omitted from operation of the device, the number N exceeding the number of processors needed for one line of said scan.

Claim 15

A device according to claim 11 wherein an analog system input is connected to said input through an analog-to digital converter, and said output is connected to an analog system output through a digital-to-analog converter.

Claim 16

A device according to claim 12 wherein said analog system input is sampled at a rate which is related to a multiple of the horizontal scan rate of said raster scan, said multiple being at least equal to the number of serial video processors.

Claim 17

A device according to claim 13 wherein said number N of said set of N serial video processors exceeds the number of pixels in a horizontal scan of said raster scan.

Claim 18

A system according to claim 11 wherein each of said first and second memories comprise a dynamic random access memory having a differential sense amplifier.

Claim 19

A system according to claim 11 wherein said input register of each video processor includes a first set of bits connected to receive said multi-bit video data in parallel from said input and a second set of bits connected in parallel to outputs of a frame memory.

Claim 20

A system according to claim 16 wherein said output register of each video processor includes a first set of bits connected to transfer in parallel said multi-bit processed data from said video processor to said output and a second set of bits connected to transfer processed data in parallel to inputs of said frame memory.

Claim 21

A system according to claim 17 wherein the number N of said set of N serial video processors as is greater than the number of pixels in a horizontal scan of said raster scan, and there is a delay of at least one of said horizontal scans between input of video data to said input and the output of processed data at said output.

Claim 22

A system according to claim 18 wherein said frame memory stores processed video data for one frame of said raster scan.

Claim 23

A serial processor system for high-speed processing, containing fault-tolerant processor elements, comprising: an input for receiving digitized, multi-bit signal data; a set of N serial processors in a linear array, each one of said set of N serial processors having: an input register connected to receive said multi-bit signal data from said input; an output register connected to transfer multi-bit processed data from the serial processor; random-access memory means having data inputs and outputs connected to said input and output registers and having at least one address input; a serial ALU element having a plurality of one-bit registers and connector means to connect inputs and outputs of each said registers to data inputs and outputs of said random-access memory means, cross connect means for connecting inputs and outputs of the ALU element to the serial ALU element of adjacent serial processors on the left and right; control inputs in common with all of said set of N serial processors receiving sets of control and address bits to select operation of the multiplexer means and addressing of said random-access memory means to thereby perform one-bit serial arithmetic/logic operations simultaneously in all of said sets of N serial processors for each separate set of control and address bits; first commutator means addressing the input registers of said set of N serial processors in a repeating sequence correlated with said signal data to load said multi-bit signal data from said input into said input registers; and second commutator means addressing the output registers of said set of N serial processors in a repeating sequence to transfer processed multi-bit data to an output; control means having a multi-bit parallel output connected in common to said control inputs and address inputs for all of said serial processors to apply sequences of sets of control and address bits to said control inputs to result in high-speed processing of said multi-bit signal data. wherein each one of said set of N serial processors and each one of said first and second commutor means has by-pass means whereby selected ones of said serial video processors are omitted from operation of the device.

Claim 24

A serial processor system for high-speed processing, containing fault-tolerant processor elements, comprising: an input for receiving digitized, multi-bit signal data; a set of N serial processors in a linear array, each one of said set of N serial processors having: an input register connected to receive said multi-bit signal data from said input; an output register connected to transfer multi-bit processed data from the serial processor; random-access memory means having data inputs and outputs connected to said input and output registers and having at least one address input; a serial ALU element having a plurality of one-bit registers and connector means to connect inputs and outputs of each said registers to data inputs and outputs of said random-access memory means, cross connect means for connecting inputs and outputs of the ALU element to the serial ALU element of adjacent serial processors on the left and right; control inputs in common with all of said set of N serial processors receiving sets of control and address bits to select operation of the multiplexer means and addressing of said random-access memory means to thereby perform one-bit serial arithmetic/logic operations simultaneously in all of said sets of N serial processors for each separate set of control and address bits; first commutator means addressing the input registers of said set of N serial processors in a repeating sequence correlated with said signal data to load said multi-bit signal data from said input into said input registers; and second commutator means addressing the output registers of said set of N serial processors in a repeating sequence to transfer processed multi-bit data to an output; control means having a multi-bit parallel output connected in common to said control inputs and address inputs for all of said serial processors to apply sequences of sets of control and address bits to said control inputs to result in high-speed processing of said multi-bit signal data. wherein each one of said set of N serial processors and each one of said first and second commutor means has by-pass means whereby selected ones of said serial video processors are omitted from operation of the device.

Claim 25

A system according to claim 10 or claim 11 wherein said random-access memory means includes first and second memories comprising dynamic random-access memory having one differential sense amplifier for each of the first and second memories for each of the serial processors.

Claim 26

A system according to claim 10 or claim 11 wherein said input register of each serial processor includes a first set of bits connected to receive said multi-bit signal data from said input and second set of bits connected to outputs of an auxiliary memory.

Claim 30

A method according to claim 24 including the steps of storing processed video data from said set of output registers in a frame memory containing a set of memory cells for each pixel of all of said horizontal scans in one vertical scan of the raster scan, and transferring the stored video data to said set of input registers in synchronization with the converting of the video signal, whereby the input registers contain data from the stored frame and also converted data for the current horizontal scan.

Claim 31

A method according to claim 24 wherein, said step of performing serial arithmetic/logic operations is performed simultaneously in all of said processor elements.

Claim 32

A method according to claim 24 wherein at least two of said horizontal scans occurs between said step of storing the digital data in the one of the set of input registers and said step of transferring digital data from the set of data memories to said output register for a given pixel of one of said horizontal scans.

Claim 35

A method according to claim 28 including the steps of storing processed data from said set of output registers in a buffer memory for a period of time during which said input signal makes a complete cycle of a repeating sequence, and transferring the stored processed data to said set of input registers in synchronization with the converting of the input signal, whereby the input registers contain data from the buffer memory and also converted data for the current input signal.

Claim 36

A method according to claim 24 or claim 28 wherein said step of performing serial arithmetic/logic operations is performed simultaneously in all of said processor elements.

Claim 37

A method according to claim 24 or claim 28 wherein said set of data memories includes first and second dynamic random-access memories having sense amplifiers clocked in synchronization with clocking of said serial processor elements.