EP0322900A2 — Electrically erasable programmable read-only memo…

Claim 1

Independent Claim 265 words

A non-volatile dynamic semiconductor memory device comprising: a semiconductive substrate (42, 100, 150) having a major surface; a semiconductive well region (40, 102) formed in said surface of said substrate, said well region being provided separate from a well region in which transistors are formed to constitute a peripheral circuit of said memory device; and parallel bit lines (BL) provided above said substrate, characterized in that said device further comprises: rewritable memory cells (M) connected to said bit lines, said memory cells comprising NAND cell blocks each of which has a series array of memory cell transistors, each of said memory cell transistors having a charge accumulation layer (50), a control gate (54) and semiconductive layers (68, 70, 72, 74, 76, 78; 106, 108, 110, 112, 114, 116) formed in said well region to function as sources and drains, and said well region functioning as a surface breakdown prevention layer; and control means (12, 14) for erasing data stored in all said memory cells simultaneously during a data erase mode of said memory device and writing data into memory cells (M1 to M4) of a selected NAND cell cell block (B1) sequentially during a data write mode subsequent to the data erase mode, said control means applying, when a certain memory cell of said selected NAND cell block (B1) is subjected to writing, to said control gate of said certain memory cell a voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer (50) of said certain memory cell and said well region (40, 102).

Claim 2

Dependent Claim 265 words

A non-volatile dynamic semiconductor memory device comprising: a semiconductive substrate (42, 100, 150) having a major surface; a semiconductive well region (40, 102) formed in said surface of said substrate, said well region being provided separate from a well region in which transistors are formed to constitute a peripheral circuit of said memory device; and parallel bit lines (BL) provided above said substrate, characterized in that said device further comprises: rewritable memory cells (M) connected to said bit lines, said memory cells comprising NAND cell blocks each of which has a series array of memory cell transistors, each of said memory cell transistors having a charge accumulation layer (50), a control gate (54) and semiconductive layers (68, 70, 72, 74, 76, 78; 106, 108, 110, 112, 114, 116) formed in said well region to function as sources and drains, and said well region functioning as a surface breakdown prevention layer; and control means (12, 14) for erasing data stored in all said memory cells simultaneously during a data erase mode of said memory device and writing data into memory cells (M1 to M4) of a selected NAND cell cell block (B1) sequentially during a data write mode subsequent to the data erase mode, said control means applying, when a certain memory cell of said selected NAND cell block (B1) is subjected to writing, to said control gate of said certain memory cell a voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer (50) of said certain memory cell and said well region (40, 102).

Claim 3

Dependent Claim 49 words

The device according to claim 1, characterized in that said substrate (42, 100) has a first conductivity type, said well region (40, 102) has a second conductivity type and said semiconductive layers (68, 70, 72, 74, 76, 78; 106, 108, 110, 112, 114, 116) have the first conductivity type.

Claim 4

Dependent Claim 66 words

The device according to claim 1, characterized in that said substrate (150) and said well region (40) have a first conductivity type and said semiconductive layers (68, 70, 72, 74, 76, 78) have a second conductivity type; and wherein said device further comprises an additional well region (152) of the second conductivity type formed in said substrate (150) so as to surround said well region (40).

Claim 5

Dependent Claim 22 words

The device according to claim 3, characterized in that said well regions (40, 152) are connected to a common well potential (Vwell).

Claim 6

Dependent Claim 121 words

The device according to claim 1, characterized in that said selected NAND cell block (B1) comprises: a first selection transistor (Qs1) provided at one end of said selected NAND cell block (B1) and selectively rendered conductive for electrically connecting said selected NAND cell block (B1) to a corresponding bit line (BL1) associated therewith; and a second selection transistor (Qs2) provided at the other end of said selected NAND cell block (B1) and selectively rendered conductive for electrically connecting said selected NAND cell block (B1) to said well area (40, 102), said second selection transistor (Qs2) being rendered nonconductive during the data write mode so as to prevent leakage of current between said corresponding bit line (BL1) and said substrate (42, 100).

Claim 7

Dependent Claim 97 words

The device according to claim 1, characterized in that each of said NAND cell blocks (B) comprises: an erase gate layer (200) provided insulatingly over said substrate (42) so as to extend substantially parallel to said series array of memory cell transistors and sandwiched insulatingly by said charge accumulation layer (50) and said control gate (54) of each of said memory cell transistors, said erase gate layer (200) overlapping said charge accumulation layer (50) and said charge accumulation layer (50) and said control gate (54) being capacitively coupled to each other by said erase gate layer (200).

Claim 8

Dependent Claim 309 words

An erasable programmable read-only memory device comprising: a semiconductive substrate (42, 100, 150) having a semiconductive well layer (40, 102) formed in its major surface; parallel bit lines (BL) provided over said substrate; and parallel word lines (WL) intersecting said bit lines insulatingly, characterized by further comprising double-gate field effect transistors (M) provided at intersections of said bit lines and said word lines for functioning as memory cells, said transistors including a cell array which has a series-circuit of cell transistors constituting a NAND cell block, each of said cell transistors having semiconductor layers serving as a source and a drain thereof, an electrically floating gate layer (28) serving as a charge accumulation layer and a control gate layer (32) connected to a corresponding word line, said semiconductor layers being formed in said well layer; a field effect transistor (Qs1) provided at one end of said NAND cell block and selectively rendered conductive for serving as a first selection transistor; a field effect transistor (Qs2) provided at the other end of said NAND cell block and selectively rendered conductive for serving as a second selection transistor; and driving means (12, 14) for, when said NAND cell block (B1) is selected during a data write mode of said device, rendering said first selection transistor (Qs1) conductive to electrically connect said NAND cell block to a corresponding bit line (B1) associated therewith to which write data is applied, rendering said second selection transistor (Qs2) nonconductive to electrically disconnect said NAND cell block from said well layer, and writing data into memory cells (M1 to M4) of said NAND cell block (B1) sequentially, said driving means changing a potential (Vwell) of said well layer to have a level different from that of a potential of said well layer in a simultaneous erase mode prior to the data write mode of said device.

Claim 9

Dependent Claim 309 words

An erasable programmable read-only memory device comprising: a semiconductive substrate (42, 100, 150) having a semiconductive well layer (40, 102) formed in its major surface; parallel bit lines (BL) provided over said substrate; and parallel word lines (WL) intersecting said bit lines insulatingly, characterized by further comprising double-gate field effect transistors (M) provided at intersections of said bit lines and said word lines for functioning as memory cells, said transistors including a cell array which has a series-circuit of cell transistors constituting a NAND cell block, each of said cell transistors having semiconductor layers serving as a source and a drain thereof, an electrically floating gate layer (28) serving as a charge accumulation layer and a control gate layer (32) connected to a corresponding word line, said semiconductor layers being formed in said well layer; a field effect transistor (Qs1) provided at one end of said NAND cell block and selectively rendered conductive for serving as a first selection transistor; a field effect transistor (Qs2) provided at the other end of said NAND cell block and selectively rendered conductive for serving as a second selection transistor; and driving means (12, 14) for, when said NAND cell block (B1) is selected during a data write mode of said device, rendering said first selection transistor (Qs1) conductive to electrically connect said NAND cell block to a corresponding bit line (B1) associated therewith to which write data is applied, rendering said second selection transistor (Qs2) nonconductive to electrically disconnect said NAND cell block from said well layer, and writing data into memory cells (M1 to M4) of said NAND cell block (B1) sequentially, said driving means changing a potential (Vwell) of said well layer to have a level different from that of a potential of said well layer in a simultaneous erase mode prior to the data write mode of said device.

Claim 10

Dependent Claim 65 words

The device according to claim 7, characterized in that said driving means writes data into memory cells (M1 to M4) of said NAND cell block (B1) in a predetermined sequence in which a cell transistor (M4) adjacent to said second selection transistor (Qs2) is subjected to writing first and a cell transistor (M1) adjacent to said first selection transistor (Qs1) is subjected to writing last.

Claim 11

Dependent Claim 90 words

The device according to claim 8, characterized in that said driving means applies, when a certain memory cell of said NAND cell block (B1) is subjected to writing, to said control gate of said certain memory cell a first voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer (50) of said certain memory cell and said well layer (40, 102) and to the remaining memory cells of said NAND cell block a second voltage lower than the first voltage.

Claim 12

Dependent Claim 49 words

The device according to claim 9, characterized in that said substrate (42, 100) has a first conductivity type, said well layer (40, 102) has a second conductivity type and said semiconductive layers (68, 70, 72, 74, 76, 78; 106, 108, 110, 112, 114, 116) have the first conductivity type.

Claim 13

Dependent Claim 51 words

The device according to claim 10, characterized in that said driving means applies to said well layer one of a "H" level potential and a "L" level potential during the simultaneous erase mode and the other of the "H" level potential and the "L" level potential during the data write mode.

Claim 14

Dependent Claim 66 words

The device according to claim 9, characterized in that said substrate (150) and said well layer (40) have a first conductivity type and said semiconductive layers (68, 70, 72, 74, 76, 78) have a second conductivity type; and wherein said device further comprises an additional well layer (152) of the second conductivity type formed in said substrate (150) so as to surround said well layer (40).

Claim 15

Dependent Claim 38 words

The device according to claim 12, characterized in that said driving means applies to said well layers (40, 152) a "L" level potential during the simultaneous erase mode and a "H" level potential during the data write mode.

Electrically erasable programmable read-only memory with NAND cell structure

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