Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
71 words
An electrically-programmable, low-impedance anti-fuse element disposed in an integrated circuit, including: a p-type semiconductor substrate, a first electrode comprising a diffusion region in said substrate, a dielectric layer over said diffusion region, and a second electrode over said dielectric layer, wherein said first and/or said second electrodes is heavily doped with arsenic such that a high concentration of arsenic atoms exist at the interface between said dielectric layer and said electrode.
Claim 2
Dependent Claim
71 words
An electrically-programmable, low-impedance anti-fuse element disposed in an integrated circuit, including: a p-type semiconductor substrate, a first electrode comprising a diffusion region in said substrate, a dielectric layer over said diffusion region, and a second electrode over said dielectric layer, wherein said first and/or said second electrodes is heavily doped with arsenic such that a high concentration of arsenic atoms exist at the interface between said dielectric layer and said electrode.
Claim 3
Dependent Claim
22 words
The electrically-programmable, low-impedance anti-fuse element of claim 1, wherein the first electrode comprises an n-type diffusion region in a p-type semiconductor substrate.
Claim 4
Dependent Claim
77 words
An electrically-programmable, low-impedance anti-fuse element, including: a semiconductor substrate, an insulating layer over said semiconductor substrate, a first electrode formed from a conducting material, over said insulating layer, a dielectric layer over said first electrode, and a second electrode over said dielectric layer, wherein at least one of said first and second electrodes is heavily doped with arsenic such that a high concentration of arsenic atoms exists at the interface between said dielectric layer and said electrode.
Claim 5
Dependent Claim
77 words
An electrically-programmable, low-impedance anti-fuse element, including: a semiconductor substrate, an insulating layer over said semiconductor substrate, a first electrode formed from a conducting material, over said insulating layer, a dielectric layer over said first electrode, and a second electrode over said dielectric layer, wherein at least one of said first and second electrodes is heavily doped with arsenic such that a high concentration of arsenic atoms exists at the interface between said dielectric layer and said electrode.
Claim 6
Dependent Claim
30 words
The electrically-programmable, low-impedance anti-fuse element of claim 1, 2 or 3, wherein said second electrode includes a layer of polysilicon having a thickness of from 500 to 10 000 angstroms.
Claim 7
Dependent Claim
37 words
The electrically-programmable, low-impedance anti-fuse element of claim 4, wherein said layer of polysilicon is heavily doped with arsenic such that a high concentration of arsenic exists at the interface between said second electrode and said dielectric layer.
Claim 8
Dependent Claim
27 words
The electrically-programmable, low-impedance anti-fuse element of any preceding claim, wherein the arsenic doping level in said polysilicon is from 1 x 10¹⁹ to 1 x 10²² atoms/cm³.
Claim 9
Dependent Claim
31 words
The electrically-programmable, low-impedance anti-fuse element of any preceding claim, wherein said dielectric layer includes a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion.
Claim 10
Dependent Claim
38 words
The electrically-programmable, low-impedance anti-fuse element of claim 7, wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms, and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.
Claim 11
Dependent Claim
42 words
The electrically-programmable, low-impedance anti-fuse element of claim 7 or 8, wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion, said third silicon dioxide portion preferably having a thickness of from 0 to 50 angstroms.
Claim 12
Dependent Claim
32 words
The electrically-programmable, low-impedance anti-fuse element of any one of claims 1 to 6, wherein said dielectric layer includes a layer of silicon dioxide having a thickness of from 60 to 150 angstroms.
Claim 13
Dependent Claim
32 words
The electrically-programmable, low-impedance anti-fuse element of any one of claims 1 to 6, wherein said dielectric layer includes a layer of silicon nitride having a thickness of from 60 to 200 angstroms.
Claim 14
Dependent Claim
30 words
The electrically-programmable, low-impedance anti-fuse element of any preceding claim, further including means for applying a programming voltage to said first and second electrodes from input/output pins of said integrated circuit.
Claim 15
Dependent Claim
54 words
A semiconductor structure disposed in an integrated circuit, including a plurality of electrically-programmable, low-impedance anti-fuses, each of said anti-fuses comprising an anti-fuse element in accordance with any preceding claim, at least one of said electrically-programmable, low-impedance anti-fuse elements including a controlled-radius electrically-conductive filament in said dielectric layer electrically connecting said first and second electrodes.
Claim 16
Dependent Claim
18 words
The semiconductor structure of claim 13, wherein said controlled-radius filament has a resistance of less than 300 ohms.
Claim 17
Dependent Claim
35 words
The semiconductor structure of claim 13 or 14, further including: means for applying a programming voltage to said first and second electrodes of selected ones of said anti-fuses from input/output pins of said integrated circuit.
Claim 18
Dependent Claim
270 words
A user-programmable read-only-memory array, including: a plurality of bit lines, a plurality of word lines, forming intersections with bit lines, a plurality of memory cells, one of said memory cells located at each of said intersections, each of said memory cells including an electrically-programmable, low-impedance anti-fuse element according to any one of claims 1 to 11, a transistor having a source, a drain, and a gate, one end of said anti-fuse element being connected to the one of said bit lines associated with said intersection, the other end of said anti-fuse being connected to the drain of said transistor, the source of said transistor being connected to a fixed voltage potential, and the gate of said transistor being connected to the one of said word lines associated with said intersection, a Y-address decoder having a plurality of address inputs, and a set of outputs, each of said outputs corresponding to one of said word lines in said array, said Y-address decoder operating to activate only one of said word lines for unique combination of data on said address inputs, an X-address decoder, having a plurality of address inputs, a set of outputs, and a data output each one of said outputs connected to one of said bit lines, such that only one of said bit lines is connected to said data output when a unique combination of data appears on said address inputs, means for applying a programming voltage to a selected one of said bit lines at a selected time, and means for applying said programming voltage to a selected one of said word lines at said selected time.