Patent EP0325422A2 successfully refreshed from Google Patents.
EP0325422A2
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EP
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Integrated cache unit
Assignee: Advanced Micro Devices Inc
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Filing: 1989-01-18
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Granted: —
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Expires: 2009-01-18
Abstract
Abstract Methods and apparatus are disclosed for realizing an integrated cache unit (ICU), that is a cache unit comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing applications in both Reduced Instruction Set Computers (RISC) and non-RISC architecture environments, and supports high speed processing applications in both single and multiprocessor systems. According to the preferred embodiment of the invention, an ICU is disclosed which includes 8k bytes of data, 512-20 bit words of tags, and the necessary control to fully implement cache functions. The preferred ICU has two buses, one for the processor interface and the other for a memory interface. The ICU supports single, burst and pipelined processor accesses and is capable of operating at frequencies in excess of 25 megahertz, achieving processor access times of two cycles for the first access in a sequence, and one cycle for burst mode or pipelined accesses. It can be used as either an instruction or data cache with flexible internal cache organization. A RISC processor and two ICUs (for instruction and data cache) implements a very high performance processor with 16 k bytes of cache. Larger caches can be designed by using additional ICUs which, according to the preferred embodiment of the invention, are modular. Further features include flexible and extensive multiprocessor support hardware, low power requirements, and support of a combination of bus watching, ownership schemes, software control and hardware control schemes which may be used with the novel ICU to achieve cache consistency.
Inventors
- 👤 Gigy Baror
- 👤 William Michael Johnson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 17:24
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F12/0804; G06F2212/00; G06F2212/60; G06F2212/601
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
194 words
A single chip integrated cache unit ("ICU") architecture for implementing cache functions in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communication between said memory and the ICU, comprising: (a) first means, coupled to said processor bus means, for receiving address and data signals generated by said CPU; (b) second means, coupled to said memory bus means, for receiving data signals off said memory bus means; (c) programmable cache means, including cache memory, for selectively storing signals received via said first and second means in said cache memory, for selectively retrieving stored signals to be transmitted to said processor and for selectively retrieving stored signals to be transmitted to said memory; (d) third means, coupled to said programmable cache means and said processor bus means, for outputting signals retrieved by said programmable cache memory means for transmission to said processor; and (e) fourth means, coupled to said programmable cache means and said memory bus means, for outputting signals retrieved by said programmable cache means for transmission to said memory.
Claim 2
Dependent Claim
194 words
A single chip integrated cache unit ("ICU") architecture for implementing cache functions in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communication between said memory and the ICU, comprising: (a) first means, coupled to said processor bus means, for receiving address and data signals generated by said CPU; (b) second means, coupled to said memory bus means, for receiving data signals off said memory bus means; (c) programmable cache means, including cache memory, for selectively storing signals received via said first and second means in said cache memory, for selectively retrieving stored signals to be transmitted to said processor and for selectively retrieving stored signals to be transmitted to said memory; (d) third means, coupled to said programmable cache means and said processor bus means, for outputting signals retrieved by said programmable cache memory means for transmission to said processor; and (e) fourth means, coupled to said programmable cache means and said memory bus means, for outputting signals retrieved by said programmable cache means for transmission to said memory.
Claim 3
Dependent Claim
18 words
An ICU architecture as set forth in claim 1 wherein said third means further comprises a cache bus.
Claim 4
Dependent Claim
19 words
An ICU architecture as set forth in claim 2 wherein said fourth means further comprises a memory address/data bus.
Claim 5
Dependent Claim
33 words
An ICU architecture as set forth in claim 3 which in a first mode of operation serves as a data cache and in a second mode of operation serves as an instruction cache.
Claim 6
Dependent Claim
20 words
An ICU architecture as set forth in claim 4 wherein said programmable cache means includes means for supporting multiprocessor operations.
Claim 7
Dependent Claim
14 words
An ICU architecture as set forth in claim 1 that is modular and expandable.
Claim 8
Dependent Claim
111 words
A single chip integrated cache unit ("ICU") architecture for implementing cache functions in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitates communication between said CPU and the ICU, memory and memory bus means which facilitates communication between said memory and the ICU, comprising: (a) a processor bus unit coupled to said processor bus means, for controlling an ICU/ processor bus interface; (b) a memory bus unit, coupled to said memory bus means, for controlling an ICU/memory bus interface; and (c) a programmable cache unit, coupled to both said processor bus unit, and said memory bus unit, for performing cache functions.
Claim 9
Dependent Claim
111 words
A single chip integrated cache unit ("ICU") architecture for implementing cache functions in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitates communication between said CPU and the ICU, memory and memory bus means which facilitates communication between said memory and the ICU, comprising: (a) a processor bus unit coupled to said processor bus means, for controlling an ICU/ processor bus interface; (b) a memory bus unit, coupled to said memory bus means, for controlling an ICU/memory bus interface; and (c) a programmable cache unit, coupled to both said processor bus unit, and said memory bus unit, for performing cache functions.
Claim 10
Dependent Claim
128 words
An ICU architecture as set forth in claim 7 wherein said processor bus unit further comprises: (a) first address incrementer means, coupled to said processor bus means and said programmable cache unit, for receiving, latching and incrementing address signals input from said processor bus means and for outputting address signals to said programmable cache unit to facilitate cache accesses; (b) data shifter means, coupled to said processor bus means and said programmable cache unit, for aligning data signals input from said processor bus means and for aligning data signals output by said programmable cache unit for transmission to said processor; and (c) processor bus unit control means, for synchronizing and controlling the operation of said first address incrementer means, said data shifter means and said programmable cache unit.
Claim 11
Dependent Claim
164 words
An ICU architecture as set forth in claim 7 wherein said memory bus unit further comprises: (a) a selectively enabled write buffer for buffering address and data signals being transmitted between said memory bus means and said programmable cache means; (b) memory address logic means, coupled to said memory bus means, said write buffer and said programmable cache unit, for latching and incrementing memory bus addresses input over said memory bus means and for latching and incrementing addresses for cache read operations initiated by said programmable cache means; (c) memory read buffer means, coupled to said memory bus means, said write buffer and said programmable cache means, for buffering data from said memory bus means until said programmable cache means is available for update and for supporting both prefetch and read operations; and (d) memory bus unit control means, for synchronizing and controlling the operation of said write buffer, said memory address logic means, said memory read buffer means, and said programmable cache unit.
Claim 12
Dependent Claim
22 words
An ICU architecture as set forth in claim 9 wherein said write buffer further comprises an address buffer and a data buffer.
Claim 13
Dependent Claim
229 words
An ICU architecture as set forth in claim 7 wherein said programmable cache unit further comprises: (a) a cache unit address bus, coupled to said processor bus unit and said memory bus unit, for carrying address signals; (b) a cache unit data bus, coupled to said processor bus unit and said memory bus unit, for carrying data signals; (c) memory array means, coupled to both said cache unit address bus and said cache unit data bus, for storing cached data and instruction signals; (d) tag array means, coupled to said cache unit address bus, for storing cache tags wherein each tag corresponds to a block of a predetermined number of cached words; (e) valid array means, coupled to said cache unit address bus, for storing data pertaining to the validity of each cached word; (f) block status array means coupled to said cache data bus, for storing an indication of the modified, shared and locked status of each block; (g) a set of special registers, coupled to said cache unit address bus and said cache unit data bus, for selecting programmable options, supporting cache control operations and indicating cache status information; and (h) cache unit control means, coupled to said processor bus control means and said memory bus control means, for synchronizing and controlling operations of said programmable cache unit, said processor bus unit and said memory bus unit.
Claim 14
Dependent Claim
44 words
An ICU architecture as set forth in claim 11 wherein said cache control means further comprises logic means, coupled to said cache unit address bus and said tag array, for comparing addresses on said cache unit address bus with tags in said tag array.
Claim 15
Dependent Claim
39 words
An ICU architecture as set forth in claim 12 wherein said cache control means further comprises logic means, coupled to said valid array, for determining if a particular cached word is valid at the time of a cache access.
Claim 16
Dependent Claim
42 words
An ICU architecture as set forth in claim 13 wherein said cache control means is further operative to generate hit signals for valid cache accesses and maintains and updates data stored in said set of special registers and said block status array.
Claim 17
Dependent Claim
33 words
An ICU architecture as set forth in claim 11 further comprising least recently used (LRU) array means for storing LRU bits whenever an LRU replacement algorithm is utilized by said programmable cache unit.
Claim 18
Dependent Claim
62 words
An ICU architecture as set forth in claim 11 wherein said set of special registers further comprises: (a) a chip select mapping register; (b) an instruction register; (c) an address operand register; (d) a count register; (e) an error register; (f) a status register; and (g) at least one programmable register for storing signals indicative of user selected ICU options and policies.
Claim 19
Dependent Claim
25 words
An ICU architecture as set forth in claim 16 further comprising means for supporting user selectable cache replacement policies including LRU, random and external policies.
Claim 20
Dependent Claim
33 words
An ICU architecture as set forth in claim 16 which in a first mode of operation serves as a data cache and in a second mode of operation serves as an instruction cache.
Claim 21
Dependent Claim
22 words
An ICU architecture as set forth in claim 16 further comprising means for supporting flexible multiprocessor operations and assuring cache data consistency.
Claim 22
Dependent Claim
14 words
An ICU architecture as set forth in claim 16 that is modular and expandable.
Claim 23
Dependent Claim
19 words
An ICU architecture set forth in claim 16 further comprising means for supporting variable block and sub-block size definition.
Claim 24
Dependent Claim
27 words
An ICU architecture as set forth in claim 16 further comprising means for supporting user specified, write-through, copy-back and flexible cache policies on a per access basis.
Claim 25
Dependent Claim
41 words
An ICU architecture as set forth in claim 16 further comprising means for achieving an operating frequency in excess of 25 megahertz with access time of two cycles for a first hit access and one cycle for the subsequent hit accesses.
Claim 26
Dependent Claim
33 words
An ICU architecture as set forth in claim 16 further comprising means for operating as a two way set associative cache in a first mode and direct mapped cache in a second mode.
Claim 27
Dependent Claim
16 words
An ICU architecture as set forth in claim 16 further comprising means for performing bus watching.
Claim 28
Dependent Claim
16 words
An ICU architecture as set forth in claim 16 further comprising means for caching interlock variables.
Claim 29
Dependent Claim
16 words
An ICU architecture as set forth in claim 16 further comprising means for performing preload operations.
Claim 30
Dependent Claim
33 words
An ICU architecture as set forth in claim 16 wherein said CPU is a simplified instruction processor having burst and pipelined protocols and further wherein said ICU comprises means for supporting said protocols.
Claim 31
Dependent Claim
23 words
An ICU architecture as set forth in claim 16 further comprising fault tolerance support means including means for generating and checking byte parity.
Claim 32
Dependent Claim
31 words
An ICU architecture is set forth in claim 29 wherein said fault tolerance support means further comprises means for operating said ICU in a cache master and a cache slave mode.
Claim 33
Independent Claim
213 words
A method for performing cache functions within a single chip integrated cache unit ("ICU") architecture, in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communitcation between said memory and the ICU, comprising the steps of: (a) inputting to said ICU, via first means coupled to said processor bus means, address and data signals generated by said CPU; (b) inputting to said ICU, via second means coupled to said memory bus means, data signals off said memory bus means; (c) storing, via programmable cache means that includes cache memory, data signals input to said ICU via said first and second means, in said cache memory; (d) retrieving stored data signals to be transmitted by said ICU to said processor; (e) retrieving stored data signals to be transmitted by said ICU to said memory; (f) outputting signals retrieved by said programmable cache memory means via third means coupling said programmable cache means and said processor bus means, for transmisstion to said processor; and (g) outputting signals retrieved by said programmable cache means, via fourth means coupling said programmable cache means and said memory bus means, for transmission to said memory.
Claim 34
Independent Claim
213 words
A method for performing cache functions within a single chip integrated cache unit ("ICU") architecture, in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communitcation between said memory and the ICU, comprising the steps of: (a) inputting to said ICU, via first means coupled to said processor bus means, address and data signals generated by said CPU; (b) inputting to said ICU, via second means coupled to said memory bus means, data signals off said memory bus means; (c) storing, via programmable cache means that includes cache memory, data signals input to said ICU via said first and second means, in said cache memory; (d) retrieving stored data signals to be transmitted by said ICU to said processor; (e) retrieving stored data signals to be transmitted by said ICU to said memory; (f) outputting signals retrieved by said programmable cache memory means via third means coupling said programmable cache means and said processor bus means, for transmisstion to said processor; and (g) outputting signals retrieved by said programmable cache means, via fourth means coupling said programmable cache means and said memory bus means, for transmission to said memory.
Claim 35
Dependent Claim
27 words
A method as set forth in claim 31 wherein the step of outputting signals retrieved via said third means is performed utilizing an internal ICU cache bus.
Claim 36
Dependent Claim
28 words
A method as set forth in claim 32 wherein the step of outputting signals retrieved via said fourth means is performed utilizing an internal ICU memory address/data bus.
Claim 37
Dependent Claim
42 words
A method as set forth in claim 33 further comprising the steps of: (a) enabling the ICU to operate, in a first mode, as a data cache; and (b) enabling the ICU to operate, in a second mode, as an instruction cache.
Claim 38
Dependent Claim
35 words
A method as set forth in claim 34 further comprising the step of enabling one of a plurality of cache multiprocessor support levels whenever the ICU is to be employed in a multiprocessor computing system.
Claim 39
Dependent Claim
15 words
A method as set forth in claim 35 which is performed on a modular chip.
Claim 40
Dependent Claim
33 words
A method as set forth in claim 36 further comprising the step of expanding cache memory capacity in said system by coupling a first modular ICU chip to a second modular ICU chip.
Claim 41
Independent Claim
128 words
A method for performing cache functions within a single chip integrated cache unit ("ICU") architecture, in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitates communication between said CPU and the ICU, memory and memory bus means which facilitates communication between said memory and the ICU, comprising the steps of: (a) controlling an ICU/processor bus interface from within said ICU utilizing a processor bus unit coupled to said processor bus means; (b) controlling an ICU/memory bus interface from within said ICU utilizing a memory bus unit coupled to said memory bus means; and (c) performing cache functions from within said ICU utilizing a programmable cache unit coupled to both said processor bus unit and said memory bus unit.
Claim 42
Independent Claim
128 words
A method for performing cache functions within a single chip integrated cache unit ("ICU") architecture, in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitates communication between said CPU and the ICU, memory and memory bus means which facilitates communication between said memory and the ICU, comprising the steps of: (a) controlling an ICU/processor bus interface from within said ICU utilizing a processor bus unit coupled to said processor bus means; (b) controlling an ICU/memory bus interface from within said ICU utilizing a memory bus unit coupled to said memory bus means; and (c) performing cache functions from within said ICU utilizing a programmable cache unit coupled to both said processor bus unit and said memory bus unit.
Claim 43
Dependent Claim
142 words
A method as set forth in claim 38 wherein the step of controlling said ICU/processor bus interface further comprises the steps of: (a) receiving, latching and incrementing address signals input from said processor bus means utilizing first address incrementer means coupled to said processor bus means and said programmable cache unit; (b) outputting address signals from said first incrementer means to said programmable cache unit to facilitate cache accesses; (c) aligning data signals input from said processor bus means utilizing data shifter means coupled to said processor bus means and said programmable cache unit; (d) aligning data signals output by said programmable cache unit for transmission to said processor via said data shifter means; and (e) synchronizing and controlling the operation of said first address incrementer means, said data shifter means and said programmable cache unit via processor bus unit control means.
Claim 44
Dependent Claim
166 words
A method as set forth in claim 38 wherein the step of controlling said ICU/memory bus interface further comprises the steps of: (a) buffering address and data signals being transmitted between said memory bus means and said programmable cache means in a selectively enabled write buffer; (b) latching and incrementing memory bus addresses input over said memory bus means utilizing memory address logic means, coupled to said memory bus means, said write buffer and said programmable cache unit; (c) latching and incrementing addresses for cache read operations initiated by said programmable cache means utilizing said memory address logic means; (d) buffering data from said memory bus means utilizing memory read buffer means coupled to said memory bus means, said write buffer and said programmable cache means, until said programmable cache means is available for update; (e) synchronizing and controlling the operation of said write buffer, said memory address logic means, said memory read buffer means, and said programmable cache unit via memory bus unit control means.
Claim 45
Dependent Claim
235 words
A method as set forth in claim 38 wherein said step of performing cache functions utilizing a programmable cache unit further comprises the steps of: (a) carrying address signals within said ICU on an internal cache unit address bus coupled to said processor bus unit and said memory bus unit; (b) carrying data signals within said ICU on an internal cache unit data bus coupled to said processor bus unit and said memory bus unit; (c) storing data and instruction signals to be cached, in memory array means coupled to both said cache unit address bus and said cache unit data bus; (d) storing cache tags in tag array means coupled to said cache unit address bus, wherein each tag corresponds to a block of a predetermined number of cached words; (e) storing data pertaining to the validity of each cached word in valid array means coupled to said cache unit address bus; (f) storing an indication of the modified, shared and locked status of each block in block status array means coupled to said cache data bus; (g) utilizing a set of special registers, coupled to said cache unit address bus and said cache unit data bus, for selecting programmable options, supporting cache control operations and indicating cache status information; and (h) synchronizing and controlling operations of said programmable cache unit, said processor bus and said memory bus unit via cache unit control means.
Claim 46
Dependent Claim
77 words
A method as set forth in claim 41 wherein said step of synchronizing and controlling further comprises the steps of: (a) comparing addresses on said cache unit address bus with tags in said tag array; (b) determining if a particular cached word is valid at the time of a cache access; (c) generating hit signals for valid cache accesses; and (d) maintaining and updating data stored in said set of special registers and said block status array.
References Cited (Backward Citations)
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