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EP0337436A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor memory device having improved dynamic memory cell structure

Assignee: NEC Corp
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Filing: 1989-04-12
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Granted: —
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Expires: 2009-04-12
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Abstract

Abstract A semiconductor memory device having an improved storage capacitor is disclosed. The memory device comprises a dynamic memory cell which including a gating transistor having first and second semiconductor regions formed on a surface of a semiconductor substrate and opposite in conductivity type to the semiconductor substrate, a gate insulating layer formed on the surface of the substrate between the first and second regions, a gate formed on the gate insulating layer and a first insulating layer covering the surface of the gate, and a storage capacitor having a second insulating layer thicker than the first insulating layer and formed on the surface of the semiconductor substrate via the first insulating layer, the second insulating layer having a trench exposing the surface of first region, a first conductive layer formed on the side wall of trench of the second insulating layer and connected to the first region, a dielectric insulating layer formed on the first conductive layer and a second conductive layer formed on the dielectric insulating layer.

Inventors

  • 👤 Hiroshi Kotaki
  • 👤 Yasukazu Inoue

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 14:44
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/036; H10B12/31; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665; H10P; H10P32/00; H10P32/30; H10P32/302

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 202 words
A semiconductor memory device comprising a plurality of dynamic memory cells formed on a semiconductor substrate of a first conductivity type, each of said memory cells including a gating field effect transistor having first and second regions of a second conductivity type opposite to said first conductivity type and formed at a surface of said semiconductor substrate, a gate insulating layer formed on the surface of said semiconductor substrate between said first and second region, a gate electrode formed on said gate insulating layer and a first insulating layer covering a surface of said gate electrode, said first insulating layer having a first thickness, and a storage capacitor having a second insulating layer formed on the surface of said semiconductor substrate via said first insulating layer, said second insulating layer having a second thickness larger than said first thickness and having a first trench exposing the surface of said first region, a first conductive layer formed on a side wall of said trench of said second insulating layer and electrically connected to said first region, a dielectric insulating layer formed on a surface of said first conductive layer, and a second conductive layer formed on a surface of said dielectric insulating layer.
Claim 2
Dependent Claim 202 words
A semiconductor memory device comprising a plurality of dynamic memory cells formed on a semiconductor substrate of a first conductivity type, each of said memory cells including a gating field effect transistor having first and second regions of a second conductivity type opposite to said first conductivity type and formed at a surface of said semiconductor substrate, a gate insulating layer formed on the surface of said semiconductor substrate between said first and second region, a gate electrode formed on said gate insulating layer and a first insulating layer covering a surface of said gate electrode, said first insulating layer having a first thickness, and a storage capacitor having a second insulating layer formed on the surface of said semiconductor substrate via said first insulating layer, said second insulating layer having a second thickness larger than said first thickness and having a first trench exposing the surface of said first region, a first conductive layer formed on a side wall of said trench of said second insulating layer and electrically connected to said first region, a dielectric insulating layer formed on a surface of said first conductive layer, and a second conductive layer formed on a surface of said dielectric insulating layer.
Claim 3
Dependent Claim 55 words
The semiconductor memory device according to claim 1, in which said second insulating layer includes a second trench for exposing a surface of said second region, said memory device further comprising a conductive material filled in said second trench and electrically connected to said second region, and a digit line connected to said conductive material.
Claim 4
Dependent Claim 21 words
The semiconductor memory device according to claim 1, in which said first and second conductive layers are formed of polycrystalline silicon.
Claim 5
Dependent Claim 22 words
The semiconductor memory device according to claim 1, in which said second thickness is more than three times of said first thickness.
Claim 6
Dependent Claim 30 words
The semiconductor memory device according to claim 1, in which said first insulating layer is formed of silicon dioxide and said second insulating layer is formed of boronphosphorous silicate glass.

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